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Part Number: LM27222
We am trying to use LM27222 as a standard push pull driver, driving two N-Ch FETs into a load of 2A. The input to PWM pin is either DC or pulsed - when pulsed, its a frequency of ~ 100Hz with high period of ~100usec. The output switching needs to be fast, changing within 100nsec of the PWM input rise/fall edges. The VCC as well as PWM input levels are 5V. The high side mosfet Vin is also 5V.
My queries are:
1) Can the device handle this kind of a switching, as the datasheet mainly intends to show this only in a buck regulator configuration.
2) We will chose a low Rdson mosfet (~40mOhm) to minimize drop over the high mosfet and have almost 5V appear at the output. Is that ok?
3) There shall be no L/C configuration at the switching node SW. The output shall directly be fed to the load. Is that ok?
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I am an applications engineer with TI and will work to address your questions.
For the concern of the switching speed of the LM27222 you can refer to the timing parameters in the datasheet and figures 2 and 3 and see that the driver has very low propagation delays. In your application however without knowing the layout and gate charge of the power mosfets we cannot say if the total end requirement of 100ns switching can be met. The layout of the gate driver output to MOSFET should be kept as short as possible to minimize layout inductance. Also the LM27222 has good driving capability of 3.2A source and 4.5A sink.
The driving capability of the driver should be more than adequate to drive power MOSFET's at a 2A level.
Regarding the operating frequency of 100Hz keep in mind the bootstrap capacitor must have adequate charge to charge the mosfet gate charge and sustain the quiescent current during the on time. There is an internal 10kΩ shunt from HG to SW, which will drain the bootstrap capacitor during high-side on time. As an example, with a 0.33µF bootstrap capacitor, the voltage drop just due to the internal 10kΩ shunt will be 5V * (1 - e^-(100µs/(10kΩ * 0.33µF))) = 150mV. Consider the voltage drop of the boot diode and the voltage should be maintained over the 4V operating voltage of the driver.
In reply to Richard Herring:
Thanks for your inputs. I have attached a schematic of what we are trying to achieve. All component values are also listed. The MOSFET PMV45EN2R has a total gate charge of max 6.3nC while the diode is a schottky diode rated with a drop of 470mV at 2A. Regarding the switching time, I dont see any issue as the device delays are low with fast rise/fall times.
However, the input may be pulsed as mentioned earlier or even a continuous high/low. This should exactly reflect on the output, and we desire the OUT voltage to be as close to 5V as possible (Rdson of the mosfet is ~50mOhm). This is where I need more clarity from you, if it is doable. If not, we are also open to your suggestion to use any other TI device to achieve our desired output.
In reply to Gaurav Agrawal1:
Thank you for the schematic details. The gate charge of the MOSFET of 6.3nC is very modest or even low, so the effective gate capacitance assuming 6.3nC with 5V drive is ~1200pF. With dt=(C dV)/I the rise time with 3.2A source current would be 1.96ns. The actual driver rise time will be less due to device rise time limitations but should be no concern in the application.
The forward drop of the diode of 470mV at 2A should not apply, since the boot cap will be charging to very low, or no current. The Vf of the diode at low current is what will apply regarding the voltage drop from 5V bias to the CB-SW capacitor voltage.
We normally recommend a 10x ratio as a guideline of the VDD capacitor to the CB capacitor. So with the bootstrap capacitor at 1uF we would recommend a 10uF VDD capacitor.
The only concern I see with the application, is the requirement to drive the PWM and HG high at a DC level. For this operation there will need to be a floating bias supply for the CB to SW bias voltage. There is a 10k HG to SW pull down resistance listed in the datasheet parameters which will result in an HG bias current that will discharge the CB capacitance. If the HG needs to be maintained at a DC high level, there will need to be a high side floating bias supply.
The SN6505 1A transformer driver from TI is a good solution for a simple floating bias supply, This part has been used for the same purpose of a high side floating bias supply.
I have attached a block diagram of the SN6505 floating bias included in the diagram you provided of the LM27222 and MOSFETs. There are additional components involved for the floating bias.
I will have to look for solutions that may work with the high side PMOS drive, in a half bridge driver.
I will attach the diagram of the SN6505 for the floating bias added to your diagram provided. Sorry for any inconvenience. I have attached the file to the post.
We ordered the SN6505B and the transformer part 750315371 as listed in the datasheet and tested as per visio circuit given by you in this thread.
Results are as below:
1) The transformer gives an output of ~6.3V with an input VCC of 5.3V, though supposed to be 1:1. As per SN6505B datasheet figure 11, under light load conditions this may be possible. I dont think its an issue as LM27222 CB pin can handle this voltage.
2) We are able to achieve a continuous DC output now after the mosfets with this floating source for bootstrap as recommended by you. So this works fine.
3) When given a pulse input, the output is measured under varying capacitive load conditions ranging from 0.1uF to 1uF. The output rise time and fall time remains almost similar with changing capacitive load but there are two issues -
a) The output is slow to rise taking almost 2 microseconds - this remains same even if the capacitive load is max or min.The MOSFET used are STN3NF06L with Ciss = 340pF and Rds on ~ 100mohm. We need max about 500-600ns switching time. Fall time transition looks ok.
b) There is a lot of ringing in all cases. We tried with series resistance upto 10 ohm from IC HG/LG to mosfet gates, but to no use.
Can you please help with the above queries.
Thank you for the continued interest in the LM27222 and SN6505 products. I am an applications engineer with TI who helped with previous inquiries.
It is good to hear you have the floating bias supply working adequate for your application, and the overall function is working now.
For the slow rising and falling times. I see that on the rising edge, the signal goes high initially at a fast slew rate then is a much slower rise time. On the falling edge it looks like a similar intial fast edge then slowing down.
There are a few thing to keep in mind for the driver performance. Can you confirm the series gate resistor value? Gate resistance will slow down the rise and fall times, although I don't expect this is the limiting factor. Also can you provide a picture of the PCB layout of the driver circuit and the routing to the power MOSFET? Excessive trace length will result in higher parasitic inductance which will inhibit the rise time of the Vgs at the MOSFET. The initial fast rise time and ringing is typical of evidence of gate driver to mosfet gate and source loop inductance.
One other value to confirm, is the value of the HB capacitance? One suggestion is if the capacitance is at least 10x the total effective gate to source capacitance, is adding a high frequency ceramic capacitor in parallel with the HB capacitance. Try a 22nF to 100nF capacitance in parallel so the high frequency impedance is reduced compared to larger ceramics or other type capacitors such as electrolytic.
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