Dear Linear Regulators team
We have a schematics for TPS7A6650H-Q1 as a below.
And then, We want ENABLE pin to Low status that if 1.7V under should be make Enable pin Low immediately?
Of course We know Voltage arrange that VIL(0V~0.4) disable Enable Pin as a blow
Do you have solution and Application when if Enablie-Pin Low is under 1.7V Low status(Disable) immediately?
And,
How to control Reset Control detail as a below?
Best Regards
Gerald
Hi Gerald,
Using a resistor divider so that Ven is less than 0.4 V as you are doing is a valid way to have the LDO disabled when Vin is 1.2 V or lower. You will want to make sure that you account for resistor tolerance in setting the divider. Another common method is to use a voltage supervisor or voltage detector to drive EN. If you would like to explore the supervisor or voltage detector option, please refer to ti.com/svs
The Reset Control is described in sections 7.3.3 and 7.3.4 of the datasheet. The FET connected PG is controlled so that PG will be logic low when Vout is less than 90% of its nominal voltage and logic high when Vout is above 90% of its nominal voltage.
Very Respectfully,
Ryan
