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TPS23753A: High efficiency design using TPS23753A

na na78
Guru 16770 points
Part Number: TPS23753A
Other Parts Discussed in Thread: PMP8896, PMP9175

Hi

Our customer is considering PoE design using TPS23753A for camera application.

They already have been used to TPS23753A, so they chose it.

The output 4V/1.2A is required and the target efficiency is over 90%.

PMP8896 reference design seems to be good but this board is not purchasable for evaluation.

So I have the following question.

1. 

TPS23753AEVM-235 seems to be the same as PMP8896 reference design.

Is it reasonable to use TPS23753AEVM-235 as the way of evaluation for customer requirement?

Do you have any other solution using TPS23753A?

2.

If TPS23753AEVM-235 is good choice, we want to refer it for customer's design too.

This EVM has synchronous flyback topology to achieve high-efficiency.

So we think it is important specially to design the following part of circuit (selection of D9, D10, D11 and FET)

We could refer layout guidelines on the user guide.

Could you please tell us other point to be considered to design high efficient circuit if you can share?

(For example, Tips on BOM selection, and so on)

BestRegards

  • 0
    TI__Mastermind 40100 points

    Hi na na 78,

    Yes, TPS23753AEVM-235 is the same as PMP8896.

    As this is an older design, it is important for this gate drive topology in general that you test the VGS of the synch FET as some designers are okay with the negative edge spike (very short time) while some are not.

    Instead, I recommend using PMP9175 that uses a different gate drive circuit and clamps the negative spike. Please see below link that shows the TI Design's schematic and test report.

    I also recommend reading the below app notes that will help you with designing around the TPS23753A and also detailed layout guidelines for PoE.

     

  • 0 in reply to Darwin Fernandez
    Guru 16770 points
    Hi Darwin

    Thank you for your reply.

    I would recommend to refer PMP9175 to the customer.

    If possible, could you please tell us the disadvantage of PMP8896 in more detail, compared with PMP9175?

    BestRegards
  • 0 in reply to na na78
    TI__Mastermind 40100 points
    Hi na na78,

    The back to back zener solution for the synch FET in a flyback converter is an older topology that we used in past power supply designs. In general a zener is not very fast so under some conditions it may not clamp fast enough. It's possible for this topology that the negative spike of the synch FET gate can be below -20V (Typical FET VGS abs max) for a very short amount of time. Of course it depends on the reliability of the FET. But rather than designing around this, PMP9175 uses a better gate clamp circuit that clamps it to nearly 0V rather than around -20V.
  • 0 in reply to Darwin Fernandez
    Guru 16770 points
    Hi Darwin

    Thank you for your explanation.

    Is there an evaluation board having the gate clamp circuit like PMP9175?

    BestRegards
  • 0 in reply to na na78
    TI__Mastermind 40100 points

    Hi na na78,

    Unfortunately there is not an orderable board this reference design as it's more of a copy and paste solution since it's already been tested. Best solution would be to modify the TPS23753AEVM-235 as the EVMs have larger pads and TP points to make it easier to evaluate and modify.

    Regards,

    Darwin

  • 0 in reply to Darwin Fernandez
    Guru 16770 points
    Hi Darwin

    Thank you for reply.

    Is there layout guideline if PMP9175 is referred?
    If you can offer the point to design PMP9175, please tell us.
    (Especially, synchronous gate drive topology on secondary side)

    BestRegards
  • 0 in reply to na na78
    TI__Mastermind 40100 points
    Hi na na 78,

    All PoE design should follow a similar approach to layout. We follow these guidelines in all our EVMs and TI Designs. Please see below app note that goes into layout in detail.
    www.ti.com/.../slua469.pdf

    PMP9175 is a much newer design that has a robust gate drive circuit for a self driven synch flyback topology while maintaining high efficiency.
  • 0 in reply to Darwin Fernandez
    Guru 16770 points
    Hi Darwin

    Thank you, I understood.

    BestRegards