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2kW PFC design from two 1000W PFC modules using UCC28070

Hi,

I would like to create a power supply for an audio power amplifier developing a 1000W PFC module using the UCC28070 controller, PFC module based on the application diagram in figure 24 of the UCC28070 datasheet.

The input to the PFC module is a 48V AC signal coming from the secondary winding of a power transformer (the primary winding being connected to the mains).

The output of the PFC module will be 90V DC, capable of supplying 1000W to the load.

The UCC28070 controller will be synced externally from an FPGA.

The load is highly variable.

The PFC module will become the fundamental building block for all sorts of applications. The intention is to build power supplies of 2000W, 3000W or more using a number of PFC modules where the outputs of the modules would be connected together (outputs in parallel).

The input of each module would be connected to separate secondary windings of separate power transformers. The primary winding of each transformer could come from the same mains line or from multiple out of phase mains lines.

My questions are:

1) Can we connect the outputs of multiple PFC modules such as the ones described above?

2) Will the power delivered to the load be shared equally between the modules?

3) Each PFC module will have its own bridge rectifier and the UCC28070 controller will monitor its input voltage individually (VINAC pin through a resistor divider). On the PFC module output side, should each PFC module have its own resistor divider monitored by the VSENSE pin or should each PFC module share a common resistor divider (every VSENSE connected together to the middle point of a single resistor divider)? To me, each module having its own resistor divider is great as far reducing the VSENSE track length and improving noise immunity on the high impedance VSENSE line are concerned, but tolerances on the resistance value of the resistor divider could lead to different regulated output voltages. 1% tolerance on the resistor divider could lead to 900mV difference between each module's output (based on 90V DC output).

4) On the other side, a single resistor divider shared by all VSENSE pins of all the modules will cause the VSENSE high impedance line to have a significant length, everything but ideal in a high impedance line situation. Can this line be buffered by an opamp or would the opamp propagation delay upset the UCC28070 internal voltage regulator process, potentially leading to oscillation?

I look forward to your reply.

Raphael

  • Hi RP

    Our Applications engineer who is most familar with this part will be back in the office Monday. I have asked him to respond to your interesting application.

    Regards

    Peter

  • In reply to Peter Meaney:

    Thanks a lot Peter. I look forward to your colleague's reply. Best regards
  • In reply to RP_CH:

    Hello Raphael,
    If all of your AC sources are different then interleaving of the sources is not possible.
    Each individual module is dual phase interleaved but the overall system is not multi-phase interleaved.
    So you will not get dual phase ripple reduction instead of multi-phase ripple reduction.
    If the AC sources have a fixed phase difference between them then the output ripple is repetitive and predictable but if the AC sources are truly independent then you may see the ripple wandering with undesirable dips in the output. This may cause issues in an audio amplifier application. You can synchronize the high frequency switching but the low frequency ripple will not be synchronized.
    The issue of load sharing between modules is the same as you would expect with any power supplies with outputs commoned together.
    You can expect to achieve equal power sharing between modules only at the full load rating for each module. At lower load power the module with the highest output voltage will tend to supply a higher percentage of the load.
    You can reduce this effect by careful pcb layout and Kelvin connected load sensing.
    The UCC28070 has a 3% tolerance on VREF but you can perhaps selected on test parts by VREF.
    You could also consider using the UCC39002 load share controller since your output voltage is only 48V.
    This would perhaps be the best solution to current sharing.
    Hope this helps !
    Regards
    John
  • In reply to John Griffin1:

    Sorry. I meant to say you will get dual phase ripple reduction and not multi phase ripple reduction
  • In reply to John Griffin1:

    Hi John,

    Thank you so much for your reply. The bad news is that you confirmed my concerned regarding parallelizing PFC modules. The good news is that your confirmation forced me to rethink my design as there was too many unknowns. The good thing of reaching a dead end is that you suddenly think out of the box and it allows you to come up with a radically different solution that solves the same problem. On this occasion, I have been able to do some work downstream of the power supplies which is now allowing my design to keep all the PFC modules separate (no need to common them any more). This instantly solved all the problems as the modules become totally self-contained and independent of each other.

    Once again, thank you for your answers, your e2e forum is quite amazing.

    Best regards,

    Raphael

  • In reply to RP_CH:

    Hi Raphael,

    Glad to help.

    Regards

    John

  • In reply to John Griffin1:

    Hi John,

    Still on the same design using UCC28070, please could you let me know what the maximum propagation delay allowed for the gate driver is? I suspect that the propagation delay of the gate driver could create instability in the controller regulation system.

    Many thanks and best regards,

    Raphael 

  • In reply to RP_CH:

    Hi Raphael,
    The UCC28070 can be used at switching frequencies up to 300kHz and propagation delays are of the order of less than 100nS.
    The prop delay on the peak current limit is 60nS typical.
    The minimum gate drive pulse width is normally 500nS to 100nS and propagation delays here are not a problem at the usual switching frequencies.
    Since the overall loop bandwidth of the pfc is very slow (10Hz or so ) this will not cause a stability issue.
    Regards
    John
  • In reply to John Griffin1:

    Ok thanks a lot John!
    Best regards,
    Raphael
  • In reply to RP_CH:

    Hi John,

    The application note slua479b.pdf (UCC28070 300-W Interleaved PFC Pre-Regulator Design Review) adds a diode (Db) between Vin rectified and Vout (in parallel with the inductor and output diode). Could you please let me know why it is needed and how to specify its current capability (in relation to the output diode current capability)? 

    Many thanks and best regards,

    Raphael

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