This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

[FAQ] TPS51206: Frequently Asked Questions and Answers

Part Number: TPS51206

General Questions:

Q: What types of DDR does TPS51206 support?

A: TPS51206 supports DDR2, DDR3, DDR3L, LP DDR3 (Low power DDR3) and DDR4.

 

Q: How to calculate the power dissipation on TPS51206.

A: TPS51206 is a linear regulate, the VLDOIN current is equal to VTT current. The power dissipation on TPS51206 device can be calculated as: (VLDOIN-VTT)*Iout.

Take DDR4 application as example. VDDQ voltage is 1.2V, VTT is 0.6V, the VTT current is 1A, the power dissipation on TPS51206 is (1.2V-0.6V)*1A=0.6W.

 

Q:   TPS51206 is a 2A LDO regulator, can TPS51206 support continuous 2A DC current?

A: We don’t suggest using TPS51206 to support continuous 2A DC load for long time. With large power dissipation, the device will be heated up and VO voltage deviation may out of DDR spec. Refer to load regulation curves on datasheet page 7 for a safe DC load current.

 

Q: What’s the over current protection mode?

A: When sink/source current is higher than 2A, the sink/source current is limited and Vout will be out of regulation. When OC condition is removed, the output voltage will recovery to regulated voltage. This is non-latch protection.

 

Q: What is VTTREF tolerance, does it meet DDR4 spec?

A: The VTTREF tolerance spec at 10mA condition is available on datasheet spec table. The additional spec (+/-1% at 100uA condition, 1.2V<=VDDQSNS<=1.8V) will be added to datasheet spec table.

100uA should be large enough for DDR applications, as the Vref leakage current of each DIMM is only a few us. With +/-1% tolerance at 100uA, the VTTREF voltage meets DDR4 spec.

 

Schematic Related Questions:

Q: How to check if the schematic is correct?

A: We suggest to follow the reference design provided on datasheet section 8 (application and implementation). Below are key things to follow.

  • Minimum 10uF capacitor is required for VLDOIN and VTT. Larger capacitance is suggested for VTT for better transient performance.
  • Use a capacitor greater than 0.1uF for VDD pin.
  • 0.22uF capacitor is suggested for VTTREF pin.

 

Q: Is there a maximum limitation for VLDOIN and VO capacitor value?

A: There is no maximum limitation for VLDOIN and VO capacitor value.

 

Q: Can VTTREF pin be open if VTTREF signal is not used?

A: No, VTTREF pin can not be open. A 0.22uF capacitor is suggested for VTTREF pin.

 

Q: Should the start-up and shut down timing in datasheet figure 23 be followed strictly?

A: The timings in datasheet figure 23 are suggested. During power on, it is allowed to turn on VDD, S3 and S5 earlier than VDLOIN and VDDQSNS. During power off, it is allowed to turn off VDD, S3 and S5 earlier than VLDOIN and VDDQSNS.

 

Layout Related Questions:

Q: Is layout guideline available on datasheet?

A: Yes, the layout guideline is available on datasheet section 10. Please follow the guideline for better performance and to avoid any unexpected issue.

 

Q: How to connect TPS51206 thermal pad, GND pin and PGND pin?

A: The thermal pad is used to dissipate heat on TPS51206. It is suggested to connect thermal pad to large power ground copper plane via multiple vias. Connect GND pin and PGND pin to the thermal pad directly.

 

1 Reply

  • Please looks at this post before submitting TPS51206 questions.

    Thanks

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.