TPS7B82-Q1: Thermal impedance for TPS7B82 LDO

Hi Florin,

We provide thermal information in section 6.4 of the datasheet in table format:

Very Respectfully,

Ryan

Hello Ryan,

I am aware about the static thermal resistance parameters. This is not what I requested.

I need information about the thermal impedance (thermal resistance as a function of time of pulse duration).

Hi Florin,

Unfortunately we do not provide thermal resistance as a function of time of pulse duration. While a pulsed load will lower the junction temperature, the main advantage is for pulses less than 10s of milliseconds and the thermals are fairly saturated when pulses begin to exceed 100s of milliseconds depending on board layout.

Very Respectfully,
Ryan

Hello Ryan,

Then based on your information, for a pulse of 150ms I should take in calculation Zth,JA = Rth,JA?

How has this "saturation" point been deducted?

Hi Florin,

The saturation point is a general rule of thumb that we use; however, this point will depend on your board layout as well as the package of the LDO itself. The primary heatsink for TPS7B82-Q1, like most LDOs, is the GND plane. The more copper that you can attach directly to the LDO, the better your thermal response will be.

Yes for a pulse of 150 ms, it would be advised to use Rth,JA for your initial estimates until board specific measurements can be taken.

Very Respectfully,
Ryan

Hello Ryan,

Well then unfortunately I have an issue. Using the standard RthJA of 63.9K/W and my circuit parameters, I get 166 deg. C maximum junction temperature, which is unacceptable.
Any further ideas?

Hi Florin,

The standard RthaJA specification is modeled on a JEDEC Hi-K board. While using a standardized board helps when comparing between two different parts or packages, the JEDEC Hi-K board does not yield optimal thermal performance. The primary heatsink for TPS7B82-Q1, like most LDOs, is the GND plane. The more copper that you can attach directly to the LDO, the better your thermal response will be.

For TPS7B82-Q1 specifically, the JEDEC board does not tie the NC pins to GND and does not have much copper on the top layer of the board. If you tie the NC pins to GND and maximize your top layer GND plane, you should achieve better thermal performance.

The only other thing that you can do is to decrease the power dissipation in the LDO. Since Vout and Iout are determined by the the load, the only thing that may be able to be reduced is Vin.

If you would like help looking for another LDO that may have a lower thermal resistance, please provide your application Vin, Vout, and Iout.

Very Respectfully,
Ryan