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TPS40303: TPS 40303's Calibration and OC function

Tan Sun
Intellectual 1810 points
Part Number: TPS40303

We read datasheet of TPS40303, in Functional Block Diagram, we know after power up, IC will enter Calibration, LDRV will disable.But we have question as:

When IC quit out from "Calibration" mode, OC function will also enable, what is the work method of LDRV/OC pin?

Thanks!

  • 0
    TI__Expert 4100 points
    Hello,
    I will forward your question to an engineer responsible for this product.
    regards
    Brani
  • 0
    TI__Expert 5900 points

    Tan,

    Programmable OCP level at LDRV is from 6 mV to 150 mV at room temperature with 3000 ppm temperature coefficient to help compensate for changes in the low-side FET channel resistance as temperature increases. With a scale factor of 2, the actual trip point across the low-side FET is in the range of 12 mV to 300 mV. The accuracy of the internal current source is ±5%. Overall offset voltage, including the offset voltage of the internal comparator and the amplifier for scale factor of 2, is limited to ±8 mV.
    Maximum clamp voltage at LDRV is 340 mV to avoid turning on the low-side FET during calibration and in a prebiased condition. The maximum clamp voltage is fixed and it does not change with temperature. If the voltage drop across ROCSET reaches the 340-mV maximum clamp voltage during calibration (no ROCSET resistor included), it disables OC protection. Once disabled, there is no low-side or high-side current sensing.
    OCP level at HDRV is fixed at 450 mV with 3000-ppm temperature coefficient to help compensate for changes in the high-side FET channel resistance as temperature increases. OCP at HDRV provides pulse-by-pulse current limiting.

    Once the OCP trip point is set then pin functions as a LDRV pin. So during calibration it serves as OC pin and after calibration it serves as LDRV pin.

    Regards,

    Mathew