TPS65381A-Q1: Powering RM57L843 - Some Questions when using 24 V supply input

Hi Stomp,

Thank you for your question. 

Indeed, thermal design considerations when using a 24V input supply is of most concern.  The TPS65381A-Q1 includes a pre-regulator from input to 6V and then downstream LDOs with integrated FETs for all regulators except VDD1.  VDD1 is used to generate the core voltage and is an LDO controller with external FET, but the sense pin can also be used to monitor the output from a DCDC when thermal and efficiency concerns require such an approach.   In some cases it may be necessary to provide a pre-regulation from 24V to an intermediate voltage such as 8 to 12V to spread the power dissipation. 

Because you are using a RM57L843 needing 1.350A it will almost certainly require a DCDC for the core rail if you are using it at maximum capability for efficiency and thermal considerations. 

TI Design TIDA-00548 uses the 6V pre-regulator rail as the supply for the DCDC, TPS62170.  This is acceptable as long as the total loading on VDD6 doesn't exceed its rated 1.3A output and from 24V the thermal design of the system can keep the TPS65381A-Q1 under the maximum specified junction temperature of 150C.  In some cases alternatives may be pre-regulate the voltage from 24V into the TPS65381A-Q1 or power the core rail DCDC from the 24V directly, but that may be a large challenge depending on the variance of the 24V input to ensure the ripple on a 1.2x V rail is low enough with such a high input to output voltage ratio and minimum on times of the DCDC.

One other note, the core rail for the RM57L843 is 1.14V to 1.32V which is not a symmetrical range when the typical supply is 1.20V and the voltage monitoring from the TPS65381A-Q1 is symmetrical to the typical value.  Normally 1.23 V is chosen as typical with the TPS65381A-Q1 so the worst case the voltage monitoring would detect UV and OV are:  with VDD1 resistor divider for 1.23 V output, the VDD1_UV threshold will be between 1.1562 V and 1.2054 V (excluding tolerance of the resistors), VDD1_OV threshold will be between 1.2669 V and 1.3038 V (excluding tolerance of the resistors).  It is recommended to use 0.1% tolerance or better resistors. 

There have been a couple of other E2E posts in the past showing alternative DCDC designs for the core rail to allow flexibility in where and how the power and thermal considerations are placed on the PCB.  I have re-attached it to this E2E. 

8078.2017-02-03 TPS65381A-Q1 with External DCDC.pdf

We have also posted a thermal estimator which includes power in the external diode for VDD6 pre-regulator and FET (when using VDD1 LDO controller).  I have re-attached it as well to help make power dissipation estimates for thermal design considerations.

2016-10-12 TPS65381 Power Estimator Draft - E2E.xlsx

Please let us know if you have further questions.