UCC21520: 10kV

Hi Martin,

Thanks for the additional information. This is very helpful.

There are three major factors which constrain the use of UCC21520 (or any TI gate driver using reinforced isolation) in extremely high voltage systems: Creepage distance across the isolation barrier, time to breakdown for a given stress on the isolation barrier, and the limitations of the channel to channel voltage.

Creepage distance for UCC21520 is just over 8mm and is set by the package geometry. For the considerably high voltages you are planning to use, there is a serious hazard from arcing between primary and secondary side of the driver. Pollution degree, humidity, altitude, ambient temperature, atmospheric composition, external conformal coating dielectric strength, and other related factors should be taken into account before designing a 10kV circuit with UCC21520. I strongly recommend conformal coating, lead molding, or some other technique to maximize the creepage along the surface of the package.

Figure 1 of the UCC21520 datasheet provides the lifetime characteristics of the UCC21520 reinforced isolation capacitor for a given applied stress. If the duty cycle is held at 50% and the IC is switching between 0V and -10kV, the RMS voltage applied across the isolation barrier will be 5kV, and the expected lifetime of the isolation barrier with some margin is on the order of 10^6 seconds, or approximately 10-30 days. However, if the UCC21520 is intended to rest with 10kV across the isolation barrier while not switching, this reduces the projected lifetime of the IC to seconds. Unless the IC is switching, the potential across the isolation barrier should be held as close to 0V as possible to maximize the barrier lifetime. If this is not possible, another isolation method such as fiber optics should be considered.

Because of the high voltage in the application and the decreased creepage between channels, I do not recommend using UCC21520 in a bridge or series stack configuration in this application. If a bridge or series stack is required, consider using separate UCC21520 with the channels tied in parallel.

Regards,

Hi Martin,

Apologies for the delay, this took some investigation. TI does not make any "simple" fiber ICs, as most of our catalog is designed for telecom applications. I know that there are a few other companies (Avago/Broadcom, for example) which do make simple transmitter/receiver pairs that can be connected over arbitrary lengths of optical cable, with well-characterized propagation delay characteristics.

A fiber-optic configuration would follow the simplified schematic below. Essentially, the signal is transmitted across the isolation barrier, conditioned to generate a square driving edge, and this edge may be used to power a gate driver IC. Biasing will be tricky, but the low switching frequency and quiescent current of the gate driver/fiber receiver should make it possible to use an unconventional low-power air-gapped supply design (a solar panel and a bright lamp for example). A battery may also be an option, depending on your required uptime.

I do not know of any semiconductor switches that are both rated for 10kV and have turn-on or turn-off times <1µs. The switching circuit will probably need to be constructed out of multiple switching elements in series, with some balancing to ensure that no individual device exceeds its absolute maximum ratings. With this in mind, care should be taken to synchronize the delay between the driving sources for the switches to within a few nanoseconds. Path lengths should be equalized for the fiber optics and the gate drive. Gate drivers and fiber elements should be selected from the same date code to minimize part-to-part variations.

From there, both switching speed and settling time are determined by the source and load impedances. Minimizing the load capacitance will maximize dv/dt of the pulse edge. Minimizing source and load inductance will help to maximize di/dt, which in turn will maximize dv/dt for a given load capacitance. Note that the parasitic series inductance for many switches in series can be quite large, and additional switches in parallel may need to be considered to reduce the inductance to acceptable levels. Control of settling time is more complex, but generally a snubber circuit can be used to tune the system response as needed.

Regards,