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Part Number: TPS7H3301-SP
Hello,These 3 questions are primarily related to the 2mOhm ESR requirement for stability of this regulator. Compared to the recommended low ESR polymer capacitors used in the datasheet example, typical CWR29 grade caps can have significantly higher ESR. In some cases it becomes impractical to meet the ESR guidelines set forth because of the amount of high reliability caps it would take to get under this limit.
1.) It appears to me that the primary benefit of this filter (based on the loop responses shown in the datasheet) is to improve gain margin of the system. Without it the overall loop gain can experience a magnitude with a flat slope (after the zero introduced by the ESR) sometime after the crossover frequency and this might only be 10dB below unity gain (Figure 23). In addition the filter probably helps to address the potential problems caused by inductive peaking of the output filter's impedance that could cause the magnitude to re-cross the unity gain line without this filter. If the purpose of this filter differs from this, please explain.
2.) In simulations, I'm finding that a potential downside of this filter is that it degrades the load disturbance rejection of the VTT output. Basically the filter reduces the bandwidth of the regulator's loop and in some cases worsens the phase margin as well. So how necessary is this filter if the 2mOhm ESR requirement isn't met? Can the PSPICE model for this regulator be used reliably to predict the phase margin and stability of the VTT regulator if the ESR is greater than 2mOhm (without the R-C filter)? One concern I have with such an approach is that the datasheet doesn't provide a tolerance of the gm for this device even at a few bias points across temperature. And the SPICE model probably only give a typical gm behavior (maybe with temperature dependence). Can someone comment on what the variation of gm from part to part might be like?
3.) In my particular application, my worst case bias current is below 300mA. I'm assuming that the 2mOhm requirement is based on using the full current range of the device. Is it a fair statement that operating at lower currents could mitigate the ESR requirement some? For instance a lower bias current would likewise lower the gm of the regulator and the dc value of the open loop gain which would directly affect the gain margin of the loop.
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In reply to Daniel Hartung:
In reply to John Rodriguez:
Unfortunately the information you are asking for simply isn't specified on our end as gm isn't part of the electrical characteristics of the part.
Thus I cannot comment on the variation from part to part.
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