LMG3410-HB-EVM: Idea for suppress heat LMG3410R070 Daughter card

Hi Satoshi,

The hot inductor in your case may relate to the reasons below:
1. The saturation current of this inductor 2300HT-151-H-RC is 7.5A, whose datasheet can be found below. With 5A average output current plus the ripple, the core may be saturated.
www.bourns.com/.../2300ht_series.pdf
2. Higher rms current will increase the winding loss, increasing the winding temperature.
To solve the problem, we suggest you to change a different inductor here, or increase the switching frequency to lower down the ripple current. 100 kHz can be a good trial. The inductor temperature is close to 100C with 100 kHz.

It is hard to use this EVM to measure the high side GaN drain current, because to achieve a low loop inductance, the GaN FETs and the DC bus ceramic capacitor locate closely on board. There is no space to put a shunt resistor in the power loop on the EVM.
If you would like to design one board to evaluate the device drain current, here are my suggestions:
1. A shunt resistor can be put in series with the low side GaN, though it will increase power loop inductance and affect the performance of the GaN FET a little bit.
2. To measure high-side GaN drain current with the current shunt, be sure to use an isolated probe. A high bandwidth is also necessary to capture the high di/dt
3. If you would like to use rogowsgi coil probe, please make sure the bandwidth is high enough.
4. If you would like to check the switching waveforms under hard-switched condition, the low-side FET in the boost converter with the current shunt can provide the information. It is easier to measure current than to measure high-side GaN EFT Ids in the buck converter.

Thank you!

Hi Satoshi,

You can refer the test condition shown in Fig. 11-13.

Please let me know if you have more questions.

Thanks,

Bingyao

Hi Satoshi-san,

For your first question to add the shunt resistor:

1. The inner copper layer 2 also has the copper to connect the device source to the GND. If you want to cut the copper, you also need to cut the copper in the inner layer 2.

2. The shunt is needed to added between the low-side FET and the bus capacitors, not just the GND terminal. The position pointed only cuts the connection from the FET source to the GND terminal, which will not give the low FET current information if the shunt is inserted.

3. This method (cutting the copper and inserting a shunt) introduces large parasitic inductance into the power loop, which would induce large switching overshoot/undershoot. The results would not be true/optimal performance of GaN. It is suggested to build a new PCB with nice layout to include the current shunt

For your second question:

The termination you highlighted is connected to PGND. 

Please let me know if you have more questions.

Thank you,

Bingyao