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TPS7A6650H-Q1: Power Good (PG) pin pull up to 3.3V

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Part Number: TPS7A6650H-Q1

Hi,

We have an application where the power supervision is done by an FPGA with 3.3V IO. Is there any issue with having a pull up to 3.3V and what is the maximum value of the pull up resistor, currently 180K

Thanks

  • Hi,

    The datasheet specifies that PG should be operating between 0 V and 5.5 V. Since this is an open-drain output, this is the recommended drain-to-source voltage to ensure that the internal pull-down FET is not damaged. Since your FPGA's logic is 3.3 V, there is no issue with potentially damaging this FET.

    The pull-up resistor should be selected to ensure that the PG pin stays within logic thresholds. The lower limit ensures that PG is logic low when the internal FET is its low impedance state. From the datasheet, the internal pull-down FET will draw 0.5 mA current in this state, and the logic low threshold is 0.4 V:

    3.3 - Iol * Rpu < Vol 

    Rpu > (3.3 - 0.4) / 0.5 mA = 5.8 kOhms

    With 180 kOhms you will not have an issue. When PG is in its open drain (high impedance) state, it has a leakage current of 1 uA. The upper limit of the pull-up resistor will depend on the logic high threshold of the device using the PG output. If we denote this as Voh:

    3.3 - Ileakage * Rpu > Voh

    Using Rpu = 180 kOhms,

    3.12 > Voh

    If your device downstream from the PG pin has a logic high threshold below 3.12 V, the pull-up resistor is fine. If not, the maximum value can be calculated as follows:

    Rpu < (3.3 - Voh)/Ileakage = (3.3 - Vh) / 1 uA

    All the mentioned currents and logic thresholds are found in the Electrical Characteristics table under RESET(PG)

    Thanks,

    Gerard

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