This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TPS3852: Query on Functionality

Part Number: TPS3852

Hi,

This is Sanjay

I have developed a watchdog circuit using TPS3852G33DRBR on a General purpose Board and found not functioning. I have stopped the WDI pulse by making it continuous High or Low to get the RESET out. But, it is not generating any RESET pulse. But, Manual Reset is functioning. Please do suggest for any modificationsTPS3852G33DRBR Schematic.pdf

  • Hi Sanjay,

    TPS3852 reset output is a open drain output. Can you add a pull up resistor and try again to see if this is the cause of the problem?

    -Marcoo
  • Hi Marcoo,

    Thanks for the reply...!

    Microcontroller RESET pin has the internal pull up. So, there no pull up is required externally and Current required for the RESET is about 400 uA.

    I have disconnected it from RESET pin added a 100K Ohm resistor to the 3.8V and verified the pin. Then also it is behaving the same way...!

  • Hi Neeraja,

    Can you remove the CDW cap and try testing reset with a smaller delay. 1uF on the CWD ha a watch dog window of 77s and I am not sure if this affecting it.

    -Marcoo
  • Hi Marcoo,

    We have tested with 0.1uF and 10K Ohm resistor also, no improvement
  • Hi Neeraja,

    Sorry for the delayed response. It was US holiday. I will work with my internal team to see what can be wrong and I will update you.

    -Marcoo
  • Hi Marcoo,

    It's okay. 

    Okay, I will wait for your response. Thanks in advance.....!

  • Hi Neeraja,

    I would test using a 1nF cap to make sure the window is much smaller.
    Is WDO and SET1 tied together? or why are the nets called the same.
    Can you send scope shots of the voltage on SET1 and WDI/WDO?
    Can you short set1 to VCC. Set1 is a digital pin and it does not require a pull it, it needs a short to GND or VCC. the voltage on SET1 might not meet logic high

    -Marcoo
  • Hi Marcoo,

    Sorry for the delayed reply, because I am outstation..!

    WDO & SET1 was not tied together. SET pin is HIGH only.

    Now we have observed that WDO is not giving any pulse (Default high) if WDI (Default high) is supplied with pulse with any timing below the watchdog time out (1uF 77sec selected) and giving Low pulse for about 200mS after about 75secs after WDI input pulse is stopped.

    But, actually as the datasheet says if pulse is supplied to the WDI with in the watchdog window period it will read as a correct input. Here if we give pulse on early fault it is considering as a correct input and not asserting the output on WDO. But, it is asserting output when input to the WDI is stopped.

  • Hi Neeraja,

    Can you send me scope shots of what you feel the issue is?
    I feel we had some confusion. The WDI input will only trigger WDO. It will never trigger RESET. Do you need WDI to also pull reset low?

    -Marcoo