UCC28700: UCC28700

Hello Rajashekar,

Thank you for your interest in the UCC28700 PSR flyback controller.

Per the datasheet, the device can operate with a supply voltage ranging from 38 V (absolute maximum) down to 8.1 V (typical UVLO level).
We recommend to stay below 35 V for margin to the ABS MAX, and stay above 9 V (including ripple minimum voltage) for margin to the UVLO shutdown level. However, the VDD will need to be able to rise above 23 V (max) in order to start up. After that, the VDD can assume any voltage within the recommended 9 V to 35 V range, depending on your design requirements. But 12~15 V is a good range for lower bias supply losses.

Supply current is less than 1.5 uA before start-up, then rises to 2.1 mA typ (2.65 mA max) during thr run time, not including average MOSFET gate-charge current. Total Ivdd = Irun + Qg*Fsw, where Qg is the MOSFET gate charge and Fsw is the frequency of interest.
Of course, Idvdd will be highest at the highest switching frequency.
At very light loads, Fsw is low and Ivdd reduces to Iwait (110 uA max) between switching pulses .
It briefly resumes to Irun level + gate charge for each switching pulse, then reverts to Iwait in between to minimize bias power.

Regards,
Ulrich

Hello Rajashekar,

The answer to your question 1 depends on several design factors which in turn depend on the target specifications of the system in which the UCC28700 is to be used.  I can't give you a specific answer without this background information. 

In general, however, the auxiliary winding voltage is a reflection of the output winding voltage (during the demagnetization interval) scaled by the aux-to-sec turns ratio. For example, if your output voltage is 5V and you want 15V for Aux bias voltage, you need a 3:1 turns ratio of aux : sec windings.  This is a ratio of the turns, not necessarily the actual number of turns.  The actual number of turns depends on the total transformer power throughput, core size and core material, pri:sec ratio and other considerations.

If the output voltage changes over a range, you must select an aux:sec ratio that accommodates the minimum levels on each side.  That is, if Vout can fall to ~1.8V (as in a USB charger example, during constant current mode) and you wish to ensure that Vaux does not fall below 10V in this condition, then the aux:sec ratio must be 5.6:1.  This means that at the normal 5V output , Vaux will be around 28V.  (I am neglecting the effects of diode drops.  The datasheet procedure takes these into account.)

For your question 2: It is difficult to test the IC separately without dedicated test equipment and fixture.  This is because the DRV output depends on dynamic inputs at both CS and VS simultaneously.  It is easy enough to apply 25V to VDD to enable the IC, but the device is designed to monitor for several kinds of fault conditions, and without any switching inputs at VS and CS, it will almost immediately shut down due to a perceived fault.  The test equipment must coordinate the correct timing between start-up and the expected responses at VS and CS when a DRV pulse is issued.  Essentially, the test equipment must mimic the operation of a flyback supply in which the IC is simulating control.

When DRV goes high, the IC expects the voltage at CS to rise above a minimum value within a maximum time interval, or it will assume a fault and shut down.  (Check the datasheet for details.)  At the same time, the IC expects to see a current out of the VS pin, due to the negative voltage on the aux winding impressed across the Rs1 resistor.  If this current is not high enough for 3 switching cycles , it will shut down due to input undervoltage.  Assuming it is high enough, then the voltage knee at VS is detected at the end of the demagnetization interval (see datasheet) and the DRV pulse width is increased if the voltage is too low, or OVP is declared if it is too high for 3 cycles.   It is a complicated endeavor to test this IC independently of the converter that it is supposed to control.

I suggest to order the EVM (http://www.ti.com/tool/ucc28700evm-068) and observe the signals on the EVM while it is operating.
Of course, use and isolated power source and proper high-voltage probing and safety techniques.

Regards,
Ulrich