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Original question:

TPS3852: The voltage on pin ~MR

TPS3852: https://e2e.ti.com/support/power-management/f/196/t/722773

SelvaKumaran R
Intellectual 2355 points
Part Number: TPS3852

Hi Team,

Wanted to know what will be the voltage level at WDI pin if it is let open. We are observing 1.2V when we are not driving the signal.

Is this acceptable?

  • 0
    TI__Genius 12630 points
    SelvaKumaran,

    The WDI is a digital pin. If this pin is not being used, the WDI pin should be tied to either VDD or GND to ensure there is no increase in IDD. Putting the pin to an intermediate voltage can cause an increase in supply current because of the architecture of the digital logic gates. I imagine the WDI pin voltage will read somewhere between VDD and GND when leaving WDI floating but again this is not recommended due to the excess current wasted.

    Please let me know if you have any other questions. Thanks!

    -Michael
  • 0 in reply to Michael_DeSando
    TI__Intellectual 2355 points

    Hi Michael,

    Thanks for your reply. Most of the OS based MCU's take couple of seconds up to a minute to boot. During the time, the GPIO's will be held in either i/p or tristate. meaning the GPIO will be in open condition. When this type of GPIO is connected to WDI, do you suspect leakage on WDI pin during this period. Datasheet didn't recommend any PU or PD on this pin, but mentioned not to drive with intermediate voltage. In this case, we are not driving the pin with any other voltage. Let me know the impact of this scenario. Is this pin internally PU to ref voltage 1.2V similar to MR pin or is it a leakage?

    - Selva 

  • 0 in reply to SelvaKumaran R
    TI__Genius 12630 points
    Selva,

    Ideally in this case, you would use the SET pin to disable the watchdog during the seconds to a minute boot up time. Using a GPIO to bring SET to logic low will cause the WDI input to be ignored. Then when everything is booted up, you can bring SET back to logic high and then use the WDI normally. This also prevents the input on WDI from causing false watchdog faults during boot up.

    We do not recommend any pull-up or pull-down resistor on WDI.

    The WDI is connected internally to a logic block so not directly to a pull-up resistor. If the GPIO is in tri-state, there will be additional leakage but this is not a concern since this is only for seconds to a minute during start up and not during normal operating conditions.

    There is no issue with the configuration except there may be a watchdog fault during this start up period if no falling edge pulse arrive on WDI within the watchdog timeout.

    I hope I was able to answer your question. Let me know if you need additional information. Thanks!

    -Michael