UCC27714: LO overshoots 20VDD

Hi Richard,

Thanks for taking time to understand this issue. Yet several things do not add up especially LO overshoot under VDD not shown in TIDA-00778 operating at 40-100kHz.

Richard Herring said:

There is not a specific driver frequency that results in driver overshoot or undershoot where it may be advised to clamp the driver outputs with schottky diodes

However there may be issues NFET versus IGBT lead to LO overshoot (<20VDD). Requires datasheet be more clear presenting facts how VDD bias cap value can also lead to sustained Trr transients. That being logical deduction as recovery transients too may exceed UVLO hysteresis in cases TI gate driver engineering has not identified and lumped into claims of stray inductance as causation. Please lab check why/how competitions lower current loop differs from UCC when competitions VDD bias cap value is typically 100 times smaller!

Richard Herring said:

The overshoot or undershoot occurs at the switching transitions and as mentioned is typically caused by gate drive current loop inductance.

That claim simply does not add up as our new PCB layout is even better than competitions gate driver PCB having had much longer HO/LO traces. Also note Infineon OPTIMOS-FD far shorter Qrr is 40% better than any NFET TI tested with UCC even in power supply application NO Schottky installed HO/LO thus uses complementary paired PWM drive signals.

We use overlapping PWM drive on both HI/LI which may effect UVLO hysteresis in an unusual way if VDD bias cap is 100x larger than competitions? Has either TI study of UCC bias CAP value properly identified causation of NFET Trr transients, clearly not. The application EVM power supply does not require HO/LO Schottky, why is it so different being PWM is complement pair on HI/LI?

Delay matching UCC (tPDRM tPDFM) 20ns is problematic for overlapping PWM HI/LI signal pairs. Oddly locks MinPW >100n thus changes Cboot typical industry RC time constant stressing HS/HO junction when low value Gton/Gtoff resistor values. Datasheet claiming IGPK +/-4A (<50us PW short) is not producible with overlapping PWM signals on HI/LI inputs being restricted >100ns PW regardless of tPDRM/tPDRF (20ns). The UCC gate driver is not holding to industry typical behavior. TI should NDNR, correct flaw produce second generation UCC same pin orientation NO HI/LI >100ns PW restriction. The >100ns pulse makes no sense in light of HO/LO has no cross-conduction prevention logic.

Richard Herring said:

Regarding TIDA specific designs Vs the datasheet, the datasheet gives an example of a switching power supply application operating at higher frequency, Vs a motor drive. The guidance for bootstrap capacitance and VDD capacitance is based on switching frequency and MOSFET parameters

Yet somehow Cboot value directly changed the PW of HI input neither of which it should ever do. Leads to HO PW >10us though not a short pulse was causing very high initial startup transient voltage on B+. So the Cboot value TIDA-00778 used (1000nf) was perhaps masked by sinusoidal PWM drives on HI/LI inputs. The competitions driver versus UCC HI/LI (>100ns MinPW) increased UCC 1000n Cboot HO PW >50us where completion has NO MinPW 50ns delay matching. That is a primary difference, seemingly leads to stressing HS-HO junction causing leakage and producing very large Trr transient onto B+.   

Hi Richard,

Richard Herring said:

Recharging the boot cap is of course dependent on the switch node transitioning to close to ground, which the expectation is that HO needs to be off during this time.

Yet Cboot RC time constant (1000n) some how over rides HI PW, perhaps an incorrect attribute of the charge pump behavior, is it not? The idea is to create a floating bias voltage for the Hi side NFET, not limit HI input PW >50us in the process. That Cboot value has a concern for overlapping PWM signals duty cycles that can transition near or <0.1us. The competitions gate driver is not limiting HI/LI pulses <100ns but only via MT 50ns. Seemingly UCC is not holding to earlier industry precedence by restricting pulses <100ns that advertently effect Cboot charging cycles. Who knew <100ns pulse restriction could ever effect Cboot charge cycles? Case to NDNR or second generation fix of <100ns pules restriction, 40ns total MT seems mute point.

Richard Herring said:

The overlapping PWM drive on LI/HI should not in itself affect the UVLO thresholds of VDD or HB

I was referring to the HO output being driven to close to the HI to LI transition thereby causing NFET Miller plateau to occur to rapidly, seemingly to close to Qrr / Trr. Perhaps result of 20ns MT and overlapping PWM signals as compared to sinusoidal or complementary paired PWM HI/LI signals? The UCC seems to manifest LO overshoot just below VDD (17v) , in slow current decay the low side NFET junction acts as a saturated switch. Forget fast NFET decay mode, LO under/over shoot is 100% worse. 

Richard Herring said:

It sounds like you need the ability to overlap HO and LO driver outputs, please confirm.

No and the foot print pin out would have to be similar. Note 80-60ns dead time is concurrent on both LO/HO of same half bridge any higher dead time cause LO undershoot ringing during GToff center of PW.

BTW:

Richard Herring said:

The overlapping PWM drive on LI/HI should not in itself affect the UVLO thresholds of VDD or HB

One more point, removal of 1000n cap VDD pin 7 to COM pin 5 reduced 3v3 PWM transients often peaking >6v by 50%.

Again point being VDD bias cap pin 7 (10uf) may be causing HO/LO sustained transients? Perhaps 1000n VDD bias cap would reduce LO/HO drive ringing or even filter 23-60mHz resonance! Should we really add 2500pf TIDA-00778 show HO/LO outputs, for what reason to add more undesired gate capacitance? There is an un-clarified reason for added gate drive capacitance in that circuit, is there not?  Do lower values of VDD bias cap <10uf from varied PWM duty cycles HI cause issues on UVLO circuit to HO drive?

Ideally IGPK 4A selected for parallel NFET drives, though is it not disturbing HS-HO stressing has manifested driving <1A loads?