I need to better understand what determines when the LMR33620C will drop into PFM mode. For example, is there a threshold that the peak inductor current must cross during the upper FET on-time to keep it in PWM mode? Some other peak current mode regulators do this.
The reason I ask is if I use Webench to look at the Ops Values during different load settings, it seems to report PFM mode when the inductor current will drop below zero (diode emulation mode). Whereas, some simulations I've run using the Pspice transient model I can see the switch node waveform is in PFM mode at load currents higher than what would cause negative inductor current and will stay in PWM mode longer if I reduce the inductor value. Since Webench doesn't support a circuit simulator for this device, I was thinking it might not capture the PFM mode accurately.
I don't have actual hardware to check this (yet), so validating the model would be really helpful for setting a target inductor value.