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BUF16821-Q1: Quickly Power ON/OFF sequence application concern

Part Number: BUF16821-Q1
Other Parts Discussed in Thread: BUF16821

Hi Team,

   Here have the questions that need your help to have the comment and suggestion for the Power ON/OFF test requirement as follows:

   As attached files are the Power ON and Power OFF waveform.

      *12V is supplied to Pgamma VS pin and 3.3V is supplied to Pgamma VSD pin.  

   From D/S that the digital supply must be applied before the analog supply to avoid excessive current and power consumption, or possibly even damage to the device if left connected only to the analog supply for extended periods of time.

   Will it has any risk during power off due to it would be has about 8msec period  that VS >9V but VSD>2V?  

   If it's, then have any suggestion to avoid the damage risk?

    

  

Best regards,

Albert Lee.

  • Hi,

    I have notified our expert regarding this topic. Please notice response may be delayed due to the US holiday season.

    Thanks,
  • Hi Albert,

    The pink trace - CH3 is the voltage at BUF16821 Vs pin?
    What's the yellow trace-CH1?
    Assuming CH3 is Vs voltage, based on first picture VSD(CH2) is turned off before turning off the analog voltage Vs(CH3). This is not recommended, the analog voltage needs to be turn off before logic is turned off in order to have a controlled DAC output.
    Also I notice picture 2 and 3 don't seems to be picture1 zoom- these are different events. Time wise turn off is not exactly same.

    Regards,
    Costin
  • Hi Costin,

     Thanks.These waveforms are from the same board.

         CH1(Yellow Trace): 12V is supplied to Pgamma VS pin

         CH2(Blue Trace): 3.3V is supplied to Pgamma VSD pin.CH1

         CH3(Purple Trace) : AVDD rail is from PMIC and it's source for 12V

     Have any circuit suggestion or check points to avoid the damage risk?

        Best regards,

      Albert Lee.

  • Hi Albert,

    My suggestion is to monitor at least one output during power On/Off.
    During Vs power down the output cap voltage may exceed Vs turning on the ESD protection diode. An output current limiting resistor is needed in this condition. Best is to monitor at least one channel output to check if Vout is greater than Vs during power down.
    Also Vsd should be turned off after Vout is off. Vout will turn off when Vs<4V.

    Regards,
    Costin
  • Hi Costin,

    Many thanks for your help.

    I will check with customer to measure output.

    I am taking care this case now and hoping you could help to review the schematic.

    May I have your email address? I would like to send the schematic to you to make sure the schematic is ok from your point of view.

    Many thanks,

    Patrick

  • Hi Patrick,

    My e-mail :
    costin.cazana@ti.com
    Please e-mail me, I'll close this thread

    Regards,
    Costin