Other Parts Discussed in Thread: BUF16821
Hi Team,
Here have the questions that need your help to have the comment and suggestion for the Power ON/OFF test requirement as follows:
As attached files are the Power ON and Power OFF waveform.
*12V is supplied to Pgamma VS pin and 3.3V is supplied to Pgamma VSD pin.
From D/S that the digital supply must be applied before the analog supply to avoid excessive current and power consumption, or possibly even damage to the device if left connected only to the analog supply for extended periods of time.
Will it has any risk during power off due to it would be has about 8msec period that VS >9V but VSD>2V?
If it's, then have any suggestion to avoid the damage risk?
Best regards,
Albert Lee.