UC3843: How to Calculate and Loop Compensation in Multiloop SMPS like the TI TIDU413 200W Interleaved Flyback for Battery Charging ?

Hi Konstantin,

I have asked one of my colleagues to answer this question, but please understand that response may be delayed due to holidays. Thank you.

Regards,
Teng

Hi Konstantin,
Sorry for the delayed response.
It is difficult to answer your question without a schematic but here are a few pointers:
The voltage compensation components should be designed exactly as for normal constant output voltage operation.
The current compensation components should be designed exactly as for normal constant output current operation.
Since only one error amplifier is in control at a time there should be no interaction between the two error amplifiers provided both are stable.
The RC circuit across the opto-coupler has a time constant of 10us. This is way too high to be significant for loop compensation and is likely placed there just to filter out high frequency noise picked up by the layout.
I hope this helps.
Joe Leisten

Hi Joe, Thankyou for your reply and Happy New Year !

I am refering to the following TI Example: The RC circuit across the opto-coupler has a time constant of 10us and yiu say its way too high, but the compensation RCs Constants on both OpAmps are even Higher...

I  have never donecompensation for constant output current operation, do you have any design Examples ?

Thankyou,

Best regards,
Konstantin

I have (hopefully correct) attached my Design as pdf can you pls check the compensation components on both opamps.
Thankyou,

Konstantin

40-70W-Digital-HV-PSU.pdf

Hi Konstantin,
My suggestion would be to sense the output current left of C20/C19.
In this case you can use a simple integrator to compensate the current loop.
You do not need to worry about the fact that the current has a pulsed wave-shape because the error amplifier is an integrator and will filter this out.
The pole of the current loop should be around 1/10 of the switching frequency but can be much lower if you like.
Since you are operating in DCM the response of the plant comes within one switching cycle so it has to be stable.

Sorry In my last reply I said the time constant was way too high to be significant for the control circuit. I meant that the time constant was short so it would only have an effect at frequencies way too high to be significant for the control loop, i.e. close to the switching frequency of the power stage.
Thanks
Joe Leisten

Hi Joe, Thankyou.

I do not really understand what you mean with "to sense the output current left of C20/C19", you mean between the Transformer and C20/C19 ? or you mean High Side ?
What would be the benefit for that ?

Are there any Example Designs eventually ?

Thankyou,

Best regards,
Konstantin

Hi Konstantin,
Yes I mean between the transformer and C20/C19.
The advantage of this position is that no delay exists between the power stage peak current control and the current detection.
In other words as soon as the voltage on the COMP pin changes the sensed output current level also changes with just one switching cycle of delay.
If you detect the current between the output capacitors (as shown on the schematic) there is delay between a change in the COMP voltage level and the sensed current due to the filtering effect of the output capacitors and inductor. Then you must ensure that this delay is compensated for in the control loop design to ensure stable operation.
I am not aware of any example designs that match exactly your requirements. If it helps I can send you some papers on design of control loops but they will not match exactly your circuit.
Thanks
Joe Leisten

Hi Joe,

could you please give me an example on how to sense between the transformer and C20/C19 (Diff Amplifier ?)

Further it would be great if you could send me some papers on design of control loops and of High Output Voltage flyback designs.

Thankyou in Advance;

Konstantin

Hi Konstantin,

At the following link:
www.ti.com/.../login.shtml
There are lots of seminar papers on control. You may need to create a MyTI account in order to view them.
They are also available at this alternative link:
www.smps.us/Unitrode.html

Can you not just move the GND connection to the bottom of the transformer winding with the resistor to the right of it? In this case you should be able to use the same circuit that you already have (inverting integrator / error amplifier)
The only downside of this approach is that more voltage ripple will exist between the PSU GND and the -ve output terminal.
Hope this helps
Joe Leisten