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TPS24700: TPS24701 Gate pin shock, after 5 times it become normal

Part Number: TPS24700
Other Parts Discussed in Thread: TPS24701, INA219, TPS2066

Hi,

  When I use TPS24701, I got into trouble, when it power up, the gate pin and vcc pin shocked several times before it work normal 

My scheme is as below, the power is 5VDC

my board load is about 0.18A, when power up,the VCC and GATE pin of the chip will shock several times before it can work properly, is it normal, the power up wave is as follow:

channel 1 is GATE pin wave, channel 2 is VCC pin wave;and the out and gate pin wave is as follows:

the detail of the shock

if the phenomenon is abnormal ,what cause this problem, how can I resolve this problem, thanks

  • Hi Haifeng zhao,

    Looks like the initial inrush current (once the gate crosses threshold) into the output caps is causing the Vin to drop below UVLO Threshold and restart. This can happen if there is no sufficient capacitance at the input. Try increasing the Input Capacitance.
    In this case, the Output was able to ramp up after many retries because there is no load or minimal load. So, the output was building slightly before Vin UVLO Occurs. The Output wouldn't have ramped up if there is load.

  • Hi Haifeng Zhao,

    Do you have any more questions? If not, can we close this thread ?
  • Thanks for your reply

       I  think the chip retried many times,because when the mosfet turn on,the power supply drop, and then I increasing a 10uF input cap, the amplitude of the shock decrease, but the number of the shock did not decrease。 I continue to increase the input cap to 22uF, 1000uF, It only can decrease the amplitude, but can not decrease the number, the power supply I used also has 2 1000uF and 1 1uF Cap. I want to know how can I decrease the number of the shock, I use the TPS24701 PSPICE Modle to simulate my circuit, It only have 1 time drop, but have no shock. When I change another model power supply ,It only have 1 time shock, so I think my problem related to the power supply. The output circuit of the power supply I used is as follow:

    C202, C203:- 2 X 1000uF/10V 
    XC213, :- 1U/10V 
    XC229, 230, 206, 212:- 22nF/200V 
    L203:- 26~32uH,见下 
    XR240:- 330R

    add 3 10uF cap in the VCC, The wave on vcc pin is as follow:


    I'm sorry I did not understand the last sentence:“So, the output was building slightly before Vin UVLO Occurs. The Output wouldn't have ramped up if there is load.”Please explain it in detail. Thank you very much and best wishes to you

  • Hi Haifeng Zhao,

    How far is the input supply from the IC? Are you adding the Input Capacitors close to the input of TPS24701 ? This is to see if there is any input impedance from the source to Vcc of TPS24701.
    How much is the load during start up ? What is kind of lod? Can you check startup with No-Load?
    Can you share waveforms of TPS24701 - Vin, Vout, Gate and Iin during startup in one snapshot ?
  • Hi Praveen,

    The power supply is about 200cm from the IC, and I add the capacitor close to the vcc pin of TPS24701(parallel with c133, c147(10uF)is the capcitor that I added). When I test the waveform, I added a 30ohm resistor (R458) to GND behind the capcitor c138. The sheme is as follow

    There are some capcitors and chips connected to the VOUT, and the test waveform are as follow:

    But when I disconnected the loads from VOUT, and only had R458 be connected, the waveform became as follow:

    I'm sorry I can't test the Iin waveform since I didn't have the current probe.

    There are 6 TPS2066 chips,4 47uF CAPS, 1 10uF CAP, 1 ALC262-VC2-GR,1 INA219 connected to the VOUT.  The TPS2066 chips are disabled because EN pin 3V3 are not supplied. The scheme of TPS2066 is as follow:

  • Hi Haifeng Zhao,

    Thanks for sharing the waveforms. Below are the three reasons which can cause the gate to be pulled Low. Since you are using TPS24701, the part is retrying after latchup. From your tests it is evident that  your load is causing  Vin to dip during startup and causing the part to latch up and restart. 

    You can try doing the following and see if you can avoid the dip on Vin,

    • Add high frequency Caps close to Vcc pin, i.e. 0.1uF and 0.01uF.
    • Try to turn ON your load after PGb goes low.
    • You can try adding Gate Capacitor so that you start up with dV/dt Control as shown below. This should definitely work. Please go through page no. 21 of datasheet.

  • Hi Praveen,

       Thanks for your reply,  I think you are right.When I disconnected the load, and then added a 1000uF cap to the VOUT,the waveform became as follow

    So I think the reason why it cause this problem is I have too much capacitive load, when power up, the load drop the VCC below UVLO, then the chip latch up and restart, because the shock start when VIN is around 2.35(the TPS24701 UVLO is about 2.3V), what do you think?

    You said I can turn on my load after PGb goes low, how can I achieve this power up sequence? and a mosfet controlled by PGb? Do you have a better method?

    Can I just add Cgate without 1kohm resistor, so that it can slow down the time to turn on the mosfet? what problem it can cause?

    I have some other test waveform as follow:

    when I connected the load, the waveform I test is as follow:

    But when I removed one of the current sense resistor, the waveform changed as follow:

    How can this happen? Did the parasitic parameters of the current sense resistor can cause this or there are some other reasons, I'm confused? I used two paralleled 2512 0.005ohm current sense resistor form a 0.0025ohm resistor. The scheme is as follow:

  • Hi Haifeng Zhao,

    PGb pulls low after the drain-to-source voltage of the FET has fallen below 170 mV and a 3.4-ms deglitch delay has elapsed. Turning ON load after Vout ramps up can be done by using PGb and FET's based on your circuit implementation.
    1k Ohms resistor is recommended in series with external gate capacitor because it prevents it from slowing a fast-turnoff event.
  • Thank you very much, I've resolved the problem by add Gate Capacitor.