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BQ25504: VBAT_OK voltage thresholds far off from expectations

user4439574
Prodigy 160 points
Part Number: BQ25504

I have a design including a BQ25504 charging a capacitor on VBAT. There is a load on VSTOR, which is switched on and off using the VBAT_OK signal. I used the spreadsheet 'SLURAQ1' to calculate the resistor values for setting VBAT_UV, VBAT_OV, VBAT_OK_PROG and VBAT_OK_HYST.

The targeted values were:

VBAT_UV = 2.233V

VBAT_OV = 3.618V

VBAT_OK = 2.387V

VBAT_OK_HYST = 2.879V

I selected the resistors accordingly:

RUV1 = 5.62M

RUV2 = 4.42M

ROV1 = 5.11M

ROV2 = 4.75M

ROK1 = 4.42M

ROK2 = 4.02M

ROK3 = 1.74M

All resistors are 1% 0805 and I have double checked that they are assembled correctly. The board has been manufactured in a fab and is spotless clean.

After taking the design in operation, I noticed that the VBAT_OK signal is triggered on values far off from what I was expecting: It switches on at 3.75V and off at 2.0V. This causes huge problems because the boost converter seems to occasionally run into the overvoltage threshold, where it switches off.

What could be the reason for this? Is it typical for the signal to be this far from the set values? How could I fix this?

Let me know if you need additional information, schematics, layout or scope recordings.

Regards,

Kai

  • 0
    TI__Guru*** 143950 points
    Kai,

    The variation you are seeing is not typical. As an quick experiment to confirm that solder flux is not the issue, I suggest removing the ROK resistors, cleaning the board with alcohol to remove any solder flux and reinstall them turned on their edge. You can also confirm that the IC is sampling correctly by reproducing datasheet figure 19.
  • 0 in reply to Jeff F
    Prodigy 160 points

    Hi Jeff,

    thanks for your reply. I have 6 boards and the behaviour was consistent across them, so flux shouldn't be the issue. While reproducing figure 19 as suggested I noticed a large offset between signal ground and power ground. When connecting both together, the  thresholds are closer to the expected values.

    I understood from the datasheet and the reference layout that the ground for the voltage dividers should only be connected to pin 12 and not externally connected to the main ground. Did I read the datasheet wrong or should the voltage thresholds also be fine, when AVSS on pin 12 is not connected to the main ground (pin1 and pin13)?

    VBAT_OK_PROG is still up to 500mV off even after connecting the grounds. Could you tell me the relation between VBAT_OK_PROG and the voltage measured on the OK_PROG pin (pin 10) during sampling, i.e. while VRDIV is connected to VSTOR? What voltage (With respect to VSTOR)  should I see on the OK_PROG pin, when I aim for a VBAT_OK_PROG threshold of 2.387V?

    Could using smaller resistor work? E.g. instead of 10M use 1M total resistance for the voltage dividers in order to increase accuracy at the cost of increased quiescent current. Does VRDIV provide enough current for that?

    Cheers,

    Kai





    Cheers,
    Kai

  • 0 in reply to user4439574
    TI__Guru*** 143950 points

    Kai,

    Great news!  I will review the datasheet.  It SHOULD say that the separate ground traces still need to connect together at one point or GND pin or the power pad of the chip.

  • 0 in reply to user4439574
    TI__Guru*** 143950 points
    Kai,

    Regarding the OK_PROG voltage, it is the VRDIV sampled values per datasheet figure 20 divided down through the resistor divider. You can use smaller resistors down into the 100kohm range but at the expense of quiescent current.
  • 0 in reply to Jeff F
    Prodigy 160 points
    Hi Jeff,

    sorry if my question was unclear. The lower battery ok threshold (VBAT_OK_PROG) is still significantly lower than what I expect based on the resistor values that I have chosen. When measuring the resistors in circuit, the values are far from their nominal values, which must be due to current paths inside the BQ itself. So that doesn't really help. In order to try and get an understanding of what is going wrong, I'm measuring the voltage at the OK_PROG pin with a scope, while keeping VSTOR fixed.

    With VSTOR at 2.85V, I see 1.05V volt during the first of the two sampling pulses (Figure 19 datasheet). However, the datasheet doesn't reveal the relationship between VSTOR, the voltage on OK_PROG and the VBAT_OK_PROG threshold that I can expect. It only gives equations for the resistor values with respect to some bias voltage.

    Where I lack understanding is how the voltage on OK_PROG and OK_HYST (which are only with respect to the varying VSTOR voltage) relate to the user-requested voltage thresholds, which are obviously absolute voltage values.

    cheers
  • 0 in reply to user4439574
    TI__Guru*** 143950 points
    Hi,

    I apologize for not understanding your question. As shown in the block diagram, the OK comparators connect one side to VRDIV through a switch in order to sample VSTOR. The other side is connected to VREF, which is named VBIAS, in the electrical spec table. I apologize for the datasheet naming inconsistency. If the sampled VSTOR divided down voltage at OK_PROG is above 1.25V, then it trips and vice versa for OK_HYST.
  • 0 in reply to Jeff F
    Prodigy 160 points
    Hi Jeff,

    thanks for your explanations. Indeed the naming inconsistency made it hard to understand the block diagram.

    After changing resistors again and debugging more with a scope I think I finally understood what's going wrong and I believe it is a result of me misunderstanding the not very verbose datasheet.

    The datasheet clearly mentions that the voltage dividers are active only every 64ms. My naive assumption was that the voltages from the resistor strings are sampled and hold internally and continuously compared to the voltage on V_STOR. However, it seems that the thresholds are also only checked every 64ms and that any exceeding of thresholds in between goes completely undetected.

    In my application I have a small capacitor and a large load that I tried to switch on and off using the VBAT_OK signal. The load discharges the capacitor rapidly, e.g. by 1V in less than 50ms. The IC ignores the exceeding of any threshold within the 64ms sampling interval, which is why the capacitor gets discharged far below the desired value.

    Can you confirm that this is the actual behavior of the IC?

    Cheers,
    Kai
  • 0 in reply to user4439574
    TI__Guru*** 143950 points

    Kai,

    You are correct.  The VRDIV voltage only biases the resistor dividers every 64ms for the amplifiers and/or comparators to function.  In between VRDIV pulses, the feedback points are ignored.

    Regards,
    Jeff