LM25118-Q1: LM25118 UVLO Pull-down Resistance

Peiheng Liu

Part Number: LM25118-Q1

Greetings!

I am helping our customer to finish their schematics and PCB layout design. Here I have a question about the ‘UVLO pulldown Rds(on)’ parameter.

From my understanding this parameter should be describing a pull-down path from UVLO pin to device GND, but I am not seeing this from the block diagram section nor the UVLO feature description. Could you please share some comments about this parameter?

Great thanks for your help!

over 5 years ago

0 Youhao Xi over 5 years ago

TI__Guru 68625 points

Hi Peiheng,

Not all part is shown in the block diagram. The FET is placed across the UVLO and GND pin. Please refer to the EC table, the last row on page 6: itis 100 Ohm typical, and 200 Ohm max.

Thanks,
Youhao Xi, BCS Applications Engineering

0 Peiheng Liu over 5 years ago in reply to Youhao Xi

TI__Prodigy 620 points

Hi Youhao,

Thanks for your prompt! Would this FET conducted during normal operation? Could you please help to share the circumstance that this FET would be driven to conducted?

Peiheng.

0 Youhao Xi over 5 years ago in reply to Peiheng Liu

TI__Guru 68625 points

Hi Peiheng,

It is off during normal operation. It is only turned on when entering the hiccup mode, discharging the UVLO and then released the UVLO for ramping up to restart.

Thanks,
Youhao

0 Peiheng Liu over 5 years ago in reply to Youhao Xi

TI__Prodigy 620 points

Hi Youhao,

This info is very helpful. Thanks for your help!

Peiheng.

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LM25118-Q1: LM25118 UVLO Pull-down Resistance