• State Resolved
  • Locked Locked
  • Replies 1 reply
  • Subscribers 62 subscribers
  • Views 237 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TPSM846C23: Output capacitors consolidation

Karol Suchecki
Prodigy 60 points
Part Number: TPSM846C23

Hello,

I want to use TPSM846C32 for Xilinx Zynq FPGA (XCZU4CG).

The datasheet of power module says: the minimum required output capacitance network consists of four 47-μF (or two 100μF) ceramic capacitors plus two 470-μF.

On the Zynq side, I have numerous rails (VCCINT, VCCINT_IO, VCCBRAM, ...), each requiring proper decoupling capacitors, that I consolidated into one 0.85V rail.

My question is, if the caps required by FPGA, exceed numbers required by TPSM, do I need to have both caps required by TPSM and FPGA or can I treat them as one capacitance?

If so, does this depend on the distance between TPSM and load? In my case the distance is small - TPSM will be adjacent to FPGA.

I googled a bit but didn't find anything conclusive.

Thank you for your help.

Kind regards,
Karol

  • 0
    TI__Mastermind 28020 points

    Yes, the capacitance required by the FPGA can be included in the minimum capacitance of the power supply. You can treat them as one capacitance. The fact that the power supply is near to the load is ideal. This will help minimize any losses for this supply.