This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

UCC28780EVM-002: UCC28780 EVM Switching waveform stairs to occur Question.

Part Number: UCC28780EVM-002
Other Parts Discussed in Thread: UCC28780,

Dear support member,

I used UCC28780.
I have a question about switching waveform.

(Specification condition)
Vin:250Vac
Vout:12Vdc
Iout:2A

(Situation)
The switching waveform was measured by UCC28780 EVM-002.
The switching waveform is stepped.

(Question)
What causes the stairs to occur?
Could you teach reason?

I attached the waveform.
Could you check it?

UCC28780EVM_Question_190409.pdf


Best regard.
Bob Lee.

  • It is mostly due to the switching ringings. I noticed your scope setup with 10k points. I suggest increase the points as the points can make the ringings distortedly presented.

    Also, the EVM you mentioned is with Vout = 20V but in your file, it says, 12V. Did you change the EVM from Vout = 20 V to 12V?
  • Dear Hong Huang,

    Thank you very much for answer.

    I made a mistake in the output voltage.
    Correctly is Vout :20Vdc.

    May I ask a add question?
    UCC28780EVM-002 Fig12 was also staircase waveform was generated.

    It becomes the following.

    (Question)
    What causes the stairs to occur?
    Could you teach reason?


    Best regard.
    Bob Lee.

  • It is due to the low oscilloscope resolution which amplifies noise effect.

  • Dear Hong Huang,

    Thank you very much for reply.
    May I ask add a question?

    (Question)
    Q1.
    Does staircase VSW waveform occur in this part?


    Q2.
    Is the staircase VSW waveform occur by the Primary current?

    (I think)
    I think that staircase VSW waveform affected by the Primary current.
    I think this Primary current ringing is resonant period of LK and CCLAMP.

    It is thought that resonance by LK and CCLAMP occurs before QH turns off.
    The 8.2.2.3 Clamp Capacitor Calculation in the data sheet also describes the resonance for LK and CCLAMP.

    『If the resonance between LK and CCLAMP is designed to be completed by the time QH is turned-off, the clamp current should reach close to 0 A around three quarters of the resonant period. 』

    Q3.
    Is this idea wrong?


    Best regard.
    Bob Lee.

  • Q1.
    Does staircase VSW waveform occur in this part?

    [Reply] no, but if set = 1, then there will be partial ZVS but that is at about 20V of Vsw and not the "staircase" in your message.


    Q2.
    Is the staircase VSW waveform occur by the Primary current? 

    [Reply] No, but digital oscilloscope resolution and primary current noise can make Vsw appear staircase.

    I think that staircase VSW waveform affected by the Primary current.

    [Reply] It is due to the noise of primary current during switching as well as due to the digital oscilloscope digitizing resolution not enough.

    I think this Primary current ringing is resonant period of LK and CCLAMP.

    [Reply] Yes, but this does not make the staircase - should also be ringing like in sine-wave but the digital oscilloscope without enough sampling points causing staircase appearance.

    It is thought that resonance by LK and CCLAMP occurs before QH turns off.

    [Reply] The resonance between Lk and Cclamp happens during / after QH (PWMH) turning off, refer to Figure 18 in the datasheet to understand their correct timing.


    The 8.2.2.3 Clamp Capacitor Calculation in the data sheet also describes the resonance for LK and CCLAMP.

    『If the resonance between LK and CCLAMP is designed to be completed by the time QH is turned-off, the clamp current should reach close to 0 A around three quarters of the resonant period. 』

    [Reply] Figure 18 shows how resonance between Lk and Cclamp during QH off when design is made properly.

    Q3.

    Is this idea wrong?

    [Reply] What idea is wrong? Yours or the operation of the IC? The operation of the IC based on the principle described in the datasheet is correct and achieve high efficiency at high switching frequency.

  • Dear Hong Huang,

    Thank you very much for reply.
    May I ask add a question?


    Q2.
    Is the staircase VSW waveform occur by the Primary current?

    [Reply] No, but digital oscilloscope resolution and primary current noise can make Vsw appear staircase.

    [Add Question]
    Q2-1.
    What is primary current noise?

    Q2-2.
    How does primary current noise occur?


    Q3.
    Is this idea wrong?

    [Reply] What idea is wrong? Yours or the operation of the IC? The operation of the IC based on the principle described in the datasheet is correct and achieve high efficiency at high switching frequency.


    [Add Question]
    I explained too few.
    My idea was that 『 I think that staircase VSW waveform affected by the Primary current.』

    Even your replied also『No, but digital oscilloscope resolution and primary current noise can make Vsw appear staircase.』.

    Q3-1.
    It is called,
    is there a relationship between the primary current noise and the staircase waveform?


    Best regard.
    Bob Lee.

  • Q2-1.
    What is primary current noise?

    [Reply] when the MOSFET (QH or QL) turns on or turns off, the current starts to change at its start point or its terminate point, there are high frequency current spikes, power supply designers call these spikes "current noise" or "current spikes".

    Q2-2.
    How does primary current noise occur?

    [Reply] See above.

    Q3-1.
    It is called, 
    is there a relationship between the primary current noise and the staircase waveform?

    [Reply] You need to increase the sampling points per unit time. Let's remember a basic fact: the UCC28780 controller PWML or PWMH has only two states, output high (turn on MOSFET) or output low (turn off MOSFET). The controller PWML or PWMH does not output staircase signal. Hope this basic fact can help what caused staircase questions. 

  • Dear Hong Huang,

    Thank you very much for reply.
    May I ask add a question?


    Is the current spike waveform here?
    It becomes the following.

    The current spike waveform is visible at the same place as the staircase waveform.

    (Question)
    Is staircase waveform affected by here high frequency current spike?


    Best regard.
    Bob Lee.

  • Yes, these switching time instants cause current spikes and so add ringings to other waveforms and if digital oscilloscope sampling point and sampling rate are not adequate, the ringings appear as stair case.

  • Dear Hong Huang,

    Thank you very much for your answer.

    I have a question about current spikes.


    (Question)
    Q4.
    What component parts causes a current spike?


    I checked the previously measured current spike period.
    It was 12.5 MHz at 80 nsc.

    I used to thinking of "Lk" and "Ccram" before, and I calculated it.
    The evaluation board had a "Lk of 2.6 μF", a "Ccramp of 0.44 μF at 0.22 μF × 2", and a frequency of 148 kHz.
    Calculated formula was used at 1 / {2π SQRT(Lk × Ccramp)} .


    It is different from the spike frequency being measured.
    Calculated frequency is 148kHz,
    But measurement frequency was 12.5MHz.


    What component parts causes a current spike?

    Best regard
    Bob Lee.

  • There are several parasitic effects, or often called, parasitic parameters, that they cause transient ringing when a current is switch off or switch on. For example, the transformer has leakage inductance but also has several parasitic capacitance effects such as between turns, between turns and grounds, between difference transformer windings, also the PCB traces formed as loop have parasitic inductance (called stray inductance) and parasitic capacitance (called stray capacitance), all resistors in name are actually a combination of R+C+L. In nature, pure R and L and C are theoretical terms.

    All these parasitic effects will respond the current changes (or voltage changes) so causing spikes (either voltage or current). We can try to minimize their effect but cannot eliminate their effect.

    It is difficult to model these parasitic effects as these effects are related to the particular components in use, PCB layout, PCB material, core material, transformer structure, etc. Usually, we do not model them, while our experience can help to minimize their effects (but not able to eliminate their effect). Practically, a design will be made to tolerate some of the effects so main power conversion is achieved ok. 

  • Dear Hong Huang,

    Thank you very much for your answer.

    As your answer that 『We can try to minimize their effect but cannot eliminate their effect.』.

    May I ask add a question?

    (Question)
    I understand that there are many effect components.
    Where is the most effective part of the components?

    Best regard.
    Bob Lee.

  • The most effective way is to minimize the current loop.

  • Dear Hong Huang,

    Thank you very much for reply.

    As the current loop you are saying,
    Is the here?
    Is it below?

    (Question)
    I think the influence depends on the layout,
    but is there a way to make it smaller with parts etc?

    For example,
    The snubber constant number.
    The clamp constant number.
    The BULK capacitor number.
    etc.

    Can the influence reduce by changing the constant?


    As the current spike waveform is occur at EVM also.
    Is there a solution?


    Best regard.
    Bob Lee.

  • Yes, the current spikes exist in EVM as said the parasitic effect can be reduced but not eliminated. The design target is to achieve specified power conversion with acceptable spikes so the design target is not to eliminate the parasitic effects - this is something that needs to be clear. If your target is to eliminate the parasitic, then I do not think we can help.

    The current loops are mainly reduced by layout. For a particular design, I assume what you mentioned "constant" are these capacitors or resistors. These values are based on the design equations and design specs, then each package size of the components are determined. I do not think you can get much different but you can try.
  • Dear Hong Huang,

    Thank you very much for reply.

    I was looking for cause the stairs to occur.

    I understand  that the cause is the current spike.

    This current spike is
    when a current is switch off or switch on that
    they cause transient ringing by parasitic effects or parasitic parameters.

    They exist parasitic effects or parasitic parameters by layout.

    I target to reduce parasitic effects.
    Is there any solution other than layout as a way to reduce parasitic effects?


    Best regard.
    Bob Lee.

  • The staircase is also partially due to the digital oscilloscope not enough sampling points or not enough sampling rate. Can you try to increase the sampling points and sampling rate and re-test, or use an analog oscilloscope to retest. The staircase shown in EVM waveform was eliminated after increase the sampling points and rate.

    The layout is key to reduce the parasitic effect. I do not think there are other effective ways to reduce parasitic effects.