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TPS3852: RESETn output pulse minimum width

Peter Martin
Prodigy 200 points
Part Number: TPS3852

Hi,

We are seeing some strange behaviour around the TPS3852 in our circuit.

We are using feedback on the SET1 pin to enable and disable the watchdog. We have seen that disabling via SET1 during an active WDO event, terminated the event. This was as described in a previous answer.

However, we are also seeing that under certain conditions the RESET output is also shortened and not the standard 200ms duration.

Can you confirm if this is possible and what is the mechanism?

Thanks Pete

  • 0
    TI__Genius 9375 points
    Hi Peter,

    I am a little confused with your question. Are you referring to tRST dropping below 200ms as specified in the datasheet? Is this happening after you
    are disabling via SET1 or are you noticing this despite doing this. Can you also further explain your "certain conditions"?

    Thanks,
    Abhinav Sharma.
  • 0 in reply to Abhinav.Sharma
    Prodigy 200 points

    Hi Abhinav,

    Yes the tRST time is not met. It is not 200ms, but can be a spike of minimum width.

    We are using the WDO output to disable a 3V3 power supply. This 3V3 power supply is connected to the MR input via a resistor. This is the route via which we are generating the RESET output.

    The VDD input is always 5V, so the TPS3852 is always powered. So we are not using the voltage threshold detector on this pin to generate the RESET. However, when we do, at power up, tRST is 200ms as advertised.

    So in the circuit, we get a watchdog event which generates WDO. This disables the 3V3 supply which is connected to the MR input. When this supply drops below about 2V? we get a RESET output that we use to disable the watchdog by setting the SET input to zero.

    This re-enables the 3V3 supply and the circuit starts working again. However, because the RESET has vanished, the circuit does not get a reset and does not initialise properly.

    Therefore, the original question still stands, is there a mechanism when using the MR input for the tRST time to be truncated?

    Thanks, Pete

  • 0 in reply to Peter Martin
    TI__Genius 9375 points
    Peter,

    There is no specified condition in which tRST should be shorted than spec. This leads me to believe that there is most likely an error in setup and could be related to your configuration of using SET1 to enable/disable the watchdog dynamically using feedback. If you look in section 7.3.4.1 of the datasheet, there is a delay named tWD-setup which describes that if you change the watchdog to enabled using SET1, there is a minimum time to wait (150 us) before the watchdog can respond to changes on WDI. That being said, this may not be the issue here. Is there a schematic you can provide of the block you are using the TPS3852 in so I can analyze this further? The behavior you described is outside of normal operation and I have not seen it in this device before.

    Thanks,

    Abhinav Sharma.
  • 0 in reply to Peter Martin
    TI__Mastermind 28530 points
    Hi Pete,

    How is your debugging going on your design?
    Do you still have concerns with device performance?
    Do you have any unanswered questions on device characteristics and/or performance?

    Let us know how we can help out :)
  • 0 in reply to Marshall_Beck
    Prodigy 200 points

    This problem is now resolved. There is no problem with the TPS3852.

    I mentioned that we were using the watchdog function to control the 3V3 power to another circuit. This circuit contains a microprocessor (STM32F family). It was this device which was driving the RESETn when it detected a brown out on the 3V3 supply. This was too short (20us) to re-initiliase the microprocessor, but long enough to reset the watchdog circuit, before the TPS3852 MRS input was triggered.

    We fixed it by adding a time delay in the watchdog circuit, but you could also split the RESETn net into separate sections.

    It's worth remembering therefore, that the STM32 family reset pin is an open drain and can be driven by anything on the net, including the microprocessor itself.

    Thanks Pete