LMG3410R070: LMG3410

robin gangopadhya18

Mastermind 6050 points

Part Number: LMG3410R070
Other Parts Discussed in Thread: INA821, UCC24612, UCC24610

In SNOU140A on the app of LMG3410 circuit you have C8 .

This is powering the chip in boost-up mode, shown to be 47uF

This is huge!

In an app where everything is low power, there is low current including peaks.

Can it be selected to something nominal such as 1uF/25V MLCCor something such as 2.2uF?

Is the 47uF value due to the buckboost negative bias the chip generates internally?

Will appreciate a range of values min to max.

Pl see attached pdf of my circuit in 380V @ 300W application where we need 2 such sync switches. I only copy the relevant part of the circuit.

thnxLMG3410GNMR_APP.pdf

over 5 years ago

0 Serkan Dusmez over 5 years ago

TI__Intellectual 805 points

Hello Robin,
Since this is an EVM which is designed to operate with both isolated high side supply and also bootstrap start-up, we chose a large value.
47uF was to make sure the bootstrap capacitor C8 has enough charge when power is lost, or GaNs are switched at low frequencies such as in the burst mode.
Now how to choose this value depends on two things; charge balance in a switching cycle (depends on RC of bootstrap path and min on-time of low side GaN FET), and hold up time required in case of burst mode or loss of power. To calculate both of these you can check the operating supply current curve in the datasheet, and make sure you can charge up the capacitor at every cycle (capacitor voltage difference is equal to VDD-Vf (diodes voltage drop) - UVLO limit--> which is around 1.2-0.8V depending on the diode used.)
To measure capacitance required for hold up time;
C= I_supply (from datasheet based on the switching frequency) * hold-up time required / Delta_Vbootstrap(like shown above).
Many of the applications require more than 4.7uF.

From your schematics, I can see that low side has no VDD capacitor and high side has very small. I highly recommend to add a min of 2.2uF capacitor to the low side and 4.7uF (depends on the hold-up time) to the high side. These should be placed very close to the LMG3410 in the pcb. Please check our app note before you design the pcb.
www.ti.com/.../snoa946a.pdf

There are other issues in the schematics;
-BB inductor should be 10uH- 22uH. Schematics show 0.2uH.
-IN pin of low side GaN has no filter. Requires RC filter.
-high side GaN has wrong connections. VNeg is connected to GND. It should have been connected to 2.2uF capacitor. LPM has been pulled to 12V -but should be pulled to 5V. You can use the LDO5V output of GaN for this pull-up.
- I would not use Si826 for sending PWM signal. At current configuration, you are applying 12V to the IN pin of high side LMG3410 but max voltage of this pin is 5.5V. It will break the part. I would recommend using ISO77XX ISO78XX for PWM level shifting.
-Just for your information, 5VLDO is an output supplied by LMG3410 to be used to power up external circuits. For instance, you can use high side GaN's 5VLDO output to power secondary side of ISO77XX.

Regards,
Serkan

0 robin gangopadhya18 over 5 years ago in reply to Serkan Dusmez

Mastermind 6050 points

Serkan

thanks a lot for pointing out issues!

The spreadsheet calculations gave .2 uH & I was very happy... small.

WIll change to what you suggest.

& we agree with all your suggestions.

robin

0 robin gangopadhya18 over 5 years ago in reply to Serkan Dusmez

Mastermind 6050 points

Oh man, there were serious slips in the floating LMG3410 circuit!

BTW: found out how the inductor got wrong. Mouser has a part that shows upon entering the BRC**** as .2 uH!...then in the last sheet of the document they list all parts from that vendor!

& I took it as being the value of .2 uH!

UGH.

So very much appreciate the corrections.

I think I got them all in.

I will read the layout again but I think I got that pretty much. But who knows: I would deeply appreciate a bit of your time to comment on the routing. Particularly because I have taken it to extreme miniaturization( a subject of our IP)...which I can share on your own TI email.CORRECTED_LMG3410APP_CKT.pdf

So a review of dos-don'ts on the LMG3410 placement, vias, etc will make sure we succeed in the delivery of our first products with TI GaN & the whole series of TI parts associated with digital control.

0 robin gangopadhya18 over 5 years ago in reply to Serkan Dusmez

Mastermind 6050 points

Serkan: I got a pdf file giving essentials of the routing layers for your review. pl email me your TI address where I can email it.

0 robin gangopadhya18 over 5 years ago in reply to robin gangopadhya18

Mastermind 6050 points

Serkan: I had Jeff Mueller's ti email because he wanted to review primary side routing. I included the rectifier side routing as well. I requetsed him to share that with you as well. Pl let me know if you got it & will be waiting eagerly your comments. thnx. r

0 Serkan Dusmez over 5 years ago in reply to robin gangopadhya18

TI__Intellectual 805 points

Hi Robin,
You are welcome. A few more notes on the schematics;
1) Low side GaN still needs a dedicated VDD cap. It may be at other parts of the schematics but I haven't seen it in the portion you provided.
2) There two current transformers in the power loop. This may significantly hurt the power loop and switching performance of GaN. I would recommend to use a shunt resistor for the low side GaN and place the floating GaNs transformer out of the power loop. If you would like to leave it as is, I would recommend to slow down the transition speed by increasing the RDRV value (RDRV vs dv/dt is provided in the datasheet).

I'm closing the thread here, and we can look at your pcb file offline since you aren't able to share it here.
Thanks,
Serkan

0 robin gangopadhya18 over 5 years ago in reply to Serkan Dusmez

Mastermind 6050 points

thanks for pointing this out regarding the presence of current xmfr. In truth, I have non-magnetic options but they have delays! the resistive approach will work as well if I find a fast amp. INA821 was what I selected for that option...dropped it in favor of faster xmfr. Would you know a faster one? bear in mind, the currents sensed are used to derive sync turn ON times.
Again thanks for reviewing the pcbs

0 robin gangopadhya18 over 4 years ago in reply to Serkan Dusmez

Mastermind 6050 points

Serkan: after a lot of checking, I found out there is a way to remove the current xmfrs from the power path of both the LMG3410 in my circuit. So now the sync ON times will be derived differently with least delay as well. And the spike killer will be located at a different branch which had the same current. This reduces any risk of having GaN switching perturbation. I nevertheless put 15K for RDRV. Recall we are using GaN not to switch at high speed but to benefit from size, low parasitics . See attached.new_lmg3410ckt.pdf

0 Serkan Dusmez over 4 years ago in reply to robin gangopadhya18

TI__Intellectual 805 points

Hi Robin,
The last schematics looks good to me. You have obviously found a new way so that you can get rid of the current transformers which will help with the voltage ringing. 15k for the RDRV would get you the fastest dv/dt transition. From schematics point of view, there is no issue. As I said before, having a good layout on pcb is very important to minimize the ringing at this high dv/dt. Following the design guidelines in the app note will make sure you have a successful implementation of your GaN based converter.
www.ti.com/.../snoa946a.pdf

Thanks and let us know if you have further questions.
Regards,
Serkan

0 robin gangopadhya18 over 4 years ago in reply to Serkan Dusmez

Mastermind 6050 points

Serkan

thnx

But a reading of the d/s seemed to imply 15k gave you the slowest slew rate?

I will check again. & select the value for giving us slow switching speed.inserted in my

Could you comment on my adoption of EPC2034 as sync switch driven by UCC24612 with a modification?

From my reading of the d/s - which I have inserted in my slides, this is totally implementable.

I got a totally unconnected response from EPC though.

In my reading of UCC24612 d/s it is quite clear that the chip provides a lot more than just ON/OFF driving signals to the MOSFET. This is a key difference with any other "just 5V " driver.

Furthermore, there is nothing inherently different in switching behavior will have between a MOSFET and a GaN.

Only difference will be strat up: but here, GaN conducts in 3rd quadrant if S is more + than Drain. Thus a "body" diode like startup will be realized until the time full diode emulation kicks in. From that time on, both switching devices will operate in a controlled manner UCC24612 senses Vds & modifies the driving output.

Agree?

robin

0 Serkan Dusmez over 4 years ago in reply to robin gangopadhya18

TI__Intellectual 805 points

Robin,
I'm not an expert in this part but in general I can say the major difference will be the VGS regulation. From the schematic of UCC24612, I can say that it should be working fine up to a certain frequency (limited by min on time) for low side FET. (Depending on the ZVS sensing time, GaN could work in third quadrant mode extensively)
But for high side with bootstrap start-up, it is very risky for GaN because the VGS can't be regulated easily. Any excess voltage above 5V on the gate can reduce the reliability. That might be one of the reasons that it is not recommended. If the supply is regulated at 5V, I think it could be used with GaN up to certain frequency. There is also another part, UCC24610, which is similar but optimized to output 5V for gate of GaN. However, again 5V rail regulation is externally required. These are my thoughts and I would suggest you to open a new thread that can reach to the experts of this part to get their opinion.

You can check the expected slew rate vs RDRV from Fig.2 of the datasheet.
www.ti.com/.../lmg3410r070.pdf

Thanks,
Serkan

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LMG3410R070: LMG3410