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TPS799: Output Discharge

Cosmin P
Intellectual 1620 points
Part Number: TPS799

Hello,


The output is volatge is rated up to 6.5V, the discharge resistor is 400Ohms.
In an application with high output capacitance, without load, the capacitor's energy will dissipate in the discharge resistor

Is there a power dissipation limitation for the output discharge resistor?

Thank you

  • 0
    TI__Guru 55940 points
    Hi Cosmin,

    Please note that the pulldown in TPS799 is used only to help discharge output overshoots of 5% and is therefore only active for short a duration of time. Large output capacitance will help reduce the likelihood of the overshoot circuit engaging as the capacitor as the charging of the increased capacitance will allow the feedback loop of the regulator more time to detect the overshoot and turn off the pass FET.

    We can calculate the expected worst case power dissipation:

    As you note, the maximum nominal output voltage is 6.5 V; therefore, the pulldown resistor will engage at 1.05 x 6.5 V = 6.825 V.

    P = V^2 / R
    P = (6.825 V)^2 / 400 Ohm
    P = 116.45 mW

    Very Respectfully,
    Ryan
  • 0 in reply to Ryan Eslinger
    TI__Intellectual 1620 points
    Hello Ryan,

    This is the power loss calculation, not the IC's power dissipation capability.

    Actually in the application both Vinput and Voutput are actively pulsed to 6.5V while the output set-up voltage is 2.5V
    This means that the min350R resistor will be sinking the 18.6mA (120mW) for the pulse duration, hence the power rating limitation question.

    Obviously, all the IC dissipated power will shift to the resistor's area during the pulse events.
    What is the power capability and teperature derating for the min350R resistor?

    Alternatively, the pulsed power derating graph would allow for complete assesment ( as in SOA and max. transient thermal impedance for FETs).

    Is the overshoot reduction active if EN is low during the Vin/Vout pulse?
    If so, the dissipation pulsed can be shotened but I still need to assess the parts' stress and design margin.


    Thank you
  • 0 in reply to Cosmin P
    TI__Guru 55940 points
    Hi Cosmin,

    It is important to note that this is a low current (~19 mA) and low power dissipation. As such we would consider the risk of damage low; however, your application as described is outside of the intended application for this regulator. The intended purpose of the Overshoot Detection is to aide in transient response rather than a biased output rail. As such we have not performed characterization in order to provide a Reliability FIT curve for your use case.

    Very Respectfully,
    Ryan
  • 0 in reply to Ryan Eslinger
    TI__Intellectual 1620 points
    Hello Ryan,

    Understood.
    Two questions left:

    1. Is the resistor disconnected at all times (regardless Vout) if EN is LOW?
    2. As the LDO was intended in its rating, is 0.4ms an acceptable time for the resistor to be ON during a transient ?

    Thank you
  • 0 in reply to Cosmin P
    TI__Guru 55940 points
    Hi Cosmin,

    The Overshoot Detection circuitry can be active regardless of Ven.

    The Overshoot Detection circuitry was designed to aide in transient overshoots only not a biased output. We do not have FIT data available; however, we again find it low risk due to the low power dissipation.

    Very Respectfully,
    Ryan