According to data sheet, the gate capacitor Cgate is calculated by equation 15. An intrinsic capacitor Cintrs is deducted from the first term. In the text above, the value of Cintrs is stated to be about 175pF.
In the design tool (TPS2475x_Design_Calculator_LowVin_Rev-.xls), Cgate is calculated in line 71. There, this Cintrs is a totally different value, calculated from (22nC / 5.8V), values taken from lines 24 and 26, respectively. That equals to 3.8nF. As a consequence, my intended slew rate of 10V/ms (leading to 0.5A loading the output capacitor of 50µF) even leads to a negative Cgate.
Since a reasonable result is achieved by the example of using 4.7nF as Cgate in the data sheet (measurement in figure 44), I think that the design tool is wrong.
Could you please advise as a quick fix if I just can use the 175pF for the second term in line 71 of the design tool, or is there a more global error with the gate charge of 22nF (line 24)?
One note to the accuracy of the dV/dt control. Looking at the measurement of the example in the data sheet (figure 44) it seems that the actual output slew rate is about twice as high as expected (expectation would be 7V/ms according to equation 15 and assuming 175pF is correct). Does it make sense to correct the calculated Cgate by this empiric factor of 2 (means use twice the calculated value), or is there just a large variation of FET parameters in the production of the device?
