Ulrich, I would still be interested to know what the rough bandwidth of the Vdd(OVP) detector is. This would also be a useful spec to add to the datasheet, in addition to the minimum output capacitance PID-loop dominant pole requirement.
I suspect that the detector is pretty wideband, which would require an adequate margin of safety to prevent spurious tripping due to feedforward (Miller cap effect) through the FET gate driver for example. This type of transient induced on Vdd during FET switching transitions might be a few tens of ns in width typically. Can you confirm that this narrow a transient on Vdd could trip Vdd OVP? This would be useful to know with certainty.
