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TPS3808: Reset Timing

Divy
Intellectual 380 points
Part Number: TPS3808

Hi , 

While  referring to the TPS3808 reset  timing diagram on Page 7 of datasheet, require the following clarifications.

In the design VDD is set to 3.3V and VIT is 1.2V.

 1.Should the VDD be Vddmin(1.7v) before  VIT+hys (sense threshold)

2.Is it Ok for VDD to be 3.3V within the reset duration. In the design when sense reaches VIT , VDD does not reach the 3.3V.

3. Once VDD is >1.7V and then Reset logic depends on VIT. Once sense pin crosses VIT , then there shall be user configured reset delay independent of Vdd and VIT power rails. Please confirm.

4.Does the MR pin accept pulse of 100ns.  In datasheet it is mentioned as 1ns (min) . Please confirm.

 

 Your quick response is highly appreciated.

  • 0
    TI__Genius 12630 points

    Divy,

    1. VDD should be VDD min whenever using the device. VIT+ hys is for the SENSE input. The SENSE input can be higher or lower than VDD upon power up but we can't guarantee the timing specs until VDD is above VDD min. The output is defined once VDD is above Vpor = 0.8V.

    2. VDD can be any voltage above VDD min regardless of the SENSE voltage. Notice the recommend voltage range for VDD and SENSE in table 7.3 do not rely on each other and are independent.

    3. Once VDD > 1.7V, /RESET output depends on MR status and SENSE pin. Correct, when SENSE rises above VIT- plus V_HYS then there is a reset time delay before RESET transitions to high.

    4. Yes MR pin accept pulse of 100ns as long as the VIL and VIH values are achieved at the bottom of Table 7.5 Electrical Characteristics.

  • 0 in reply to Michael_DeSando
    Intellectual 380 points

    Hi Michael,

    Thanks for the reply .Can you please help clarify below

    1. If MR is pulsed low for 100ns below Sense reaches VIT , then reset out will low for a user defined reset period (I kept as 150ms)? or reset is pulled low till sense reaches VIT

    2. If MR is pulsed low after Sense reaches VIT and if reset output is in the user defined reset period , reset will comes out high after 150ms(reset time)

    Thanks,

    Divy

  • 0 in reply to Divy
    TI__Genius 12630 points
    Divy,

    1. RESET is always low until SENSE is above VIT+ *and* MR is logic high. Whichever occurs last sets the reset delay timer.

    2. If MR is pulsed low while the device is already in reset, the MR pulse has no effect. Once the MR is logic high and the SENSE is above VIT+ , then the user defined reset delay starts. The reset is release back to high once the delay time expires unless one of the above conditions causes the device to remain in reset.

    Please let me know if you have additional questions. Thanks!