We’re using the TPS3808G50DBVT powered by 5V. Based on the datasheet, the MR pin has an internal pull-up resistor which is typically 90K. The datasheet provides the minimum value of 70K, but not the maximum value. An e2e case (e2e.ti.com/.../108036 MR max internal 90K resistor value) suggested adding 40% to the typical value would provide the maximum value, which would be 126K. So the internal pull-up could be anywhere between 70K and 126K.
We have not included an external pull-up resistor for our MR pin. It’s driven by an open-drain driver.
In order to ensure a working interface over all operating conditions, we must account for ALL sources of leakage current. That includes the leakage of our open-drain driver, and it necessarily includes any leakage current internal to the TPS3808 which must also flow through that internal MR resistor.
Put another way, the MR pin is likely connected to some internal buffer circuit which will have some amount of leakage current. That buffer input circuit might source or sink leakage current (more on that later). So in summary, we can talk about leakage currents as the sum of 2 leakage currents: leakage from what’s connected to the MR pin externally, and the leakage from the MR buffer input circuit. Hopefully that makes sense.
The datasheet MR pin VIH minimum is 0.7 * VDD (or 3.5V in our simple example). An e2e case (e2e.ti.com/.../1958567 MR max internal leakage current#1958567) confirmed the MR pin is not Schmitt Trigger, so there would be no guaranteed hysteresis.
That all said, we need to ensure the sum of all leakage currents flowing in that internal MR pull-up resistor won’t ever drop the voltage below 3.5V.
With the internal resistor at its maximum value of 126K, the maximum total leakage current (from all sources) that could be tolerated is (5 – 3.5) / 126K = ~ 12uA. It’s not uncommon to see maximum leakage current specifications for digital devices on the order of 10uA. So if our open-drain driver max leakage current is 10uA, that only allows around 2uA for the internal MR pin leakage.
So we finally arrive at a question. What is the worst case MR pin internal leakage current over process, voltage, temperature, and life?
On a related note, can TI tell us if the MR buffer input circuit leakage current could flow in either direction, or maybe it would not flow through the internal MR pull-up resistor? Put another way, sometimes we see +/- specifications on leakage currents, which means they could flow into or out of the device. The – sign often indicates current flowing out of the device; the + sign often means the current flows into the device. So would the leakage currents internal to the MR pin flow into the MR pin internal circuits, or out of them, or possibly both directions? The thought was that if we know those internal leakage currents are always flowing OUT of the MR buffer input circuit, then they don’t count toward the voltage drop across that internal pull-up resistor that we’re worried about, right?
Thanks in advance.
