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LMZ30606: Power Good sink current

Part Number: LMZ30606

In the situation of concern, the power good pin is pulled-up to 3.3V through 20kohms and there is a 0.1uF capacitor connected to ground.

The abs max current for the PG pin is 10mA. Is there any chance of damage to the LMZ30606 device if the PG pin goes low and discharges the 0.1uF capacitor?

What value of capacitance would cause a problem considering that 1/2 CV^2 would be dissipated int he internal pull-down FET?

  • Hi Steve,

    The PWRGD is an output drain output that is controlled through the PWRGD logic detailed in the functional block diagram in Section 5 of the datasheet.

    For 3.3V and 20kohms pull-up, the device would not hit abs max current for PG pin. I don't think it there would be an issue with the 0.1uF capacitor.

    What is the purpose of the 0.1uF on the PG pin? Only a pull-up resistor is required for the PG fault pin.

    Regards,

    Jimmy

  • Jimmy,

    We need to know if discharging the 0.1uF capacitor damages the device. We have to be sure on this one.

    I believe that the cap was put there for filtering - this is on already manufactured boards that have gone through severe and lengthy validation testing and the PG has discharged the 0.1uF capacitor many times (power-up / down cycles). The question is if the device could have a latent failure due to exceeding the maximum current as the PG is pulled low and the cap is discharged into the small open-drain FET.

    The 20k resistor is not a concern so much as the 0.1uF cap. The capacitor will have ~ 500nJ of energy available - is that enough to cause damage to the part.

    Steve

  • HI Steve,

    I am waiting for more information from the IC designer on the limitation of the internal PWRGD FET. I hope to get information back from him soon and provide a reply to your question. For the way I see it, the 0.1uF and 3.3V source will result in a peak current higher than the 10mA maximum current rating of the PWRGD pin.

    Regards,

    Jimmy

  • Hi Steve,

    Unfortunately, your application will result in the PWRGD pin exceeding 10mA. This may result in EOS damage on the PWRGD structure. I would advise to remove PWRGD bypass capacitor on the board.

    Regards,

    Jimmy