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Part Number: TPS7A6650H-Q1
For the TPS7A6650-Q1, if the EN pin is low, does the PG pin still function? In other words, will PG be active low, or does PG only function when EN is high? According to the block diagram, it looks like PG needs the EN to be high, but I don’t know how accurate the block diagram is.
PG is an open drain pin. It requires an external pull up resistor connected to a regulated voltage source. If PG pin connected to the VOUT of the regulator, VPG is logic level high when VOUT is above the power-on-reset threshold. It isn't depending on the EN pin.
The PG functionality is described in the datasheet section 7.3.3. The PG output remains low until the regulated VOUT has exceeded approximately 90% of the set value and the power-on-reset delay has expired. The regulated Vout output falling below the 90% level asserts PG output low after a short de-glitch time of approximately 250 µs (typical).
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In reply to Min Hudgins:
So Power Good is actively pulled low even when EN is low or floating? Is this correct?
In reply to D:
PG pin is pulled low because of Vout falling below the threshold, not because of EN pin. If EN is low enough (< VIL max), the part will be disabled. The Vout will drop to 0V and pull the PG pin to low.
If PG is pulled up to voltage different from Vout will the device actively pull PG low when EN is low?
PG can be connected to Vout or a different voltage source via pull up resistor. It doesn't change the PG functionality. If EN is low enough (< VIL max), the part will be disabled. The Vout will drop to 0V and pull the PG pin to low.
When the EN pin was pulled low ( from 1.7V o 0.7V in my bench setup), the PG pin went low, with Vout was forced to 5V. PG pin went high when EN rising voltage was about 1.5V.
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