Hello,
I'm using a UCC27525 gate driver IC to drive the mosfets being used in the CUK converter topology attached below. A dual mosfet is being used with a NMOS and a PMOS integrated in it. My question is that what is the safe voltage range for the VDD pin to be supplied with? What i supply the VDD with is a +8v. To drive the gate of a PMOS a negative pulse should be applied to the gate and that's why i used an extra circuitry other than external gate resistor circuits as shown in the file attached below. But the problem is that as the supply voltage applied to VDD pin goes up, the inductor current and output voltage waveforms become pretty noisy. The most stable voltage current waveforms were yielded with a +8v supply voltage and belowsch1212.pdf.
Secondly, what is the value of RNMOS for this gate driver IC. Based on the datasheet the effective resistance of the hybrid pullup structure during turn on is estimated to be approximately 1.5 × ROL, estimated based on design considerations. Where is this resistance used for in IOH calculation?
Third, what is the internal operating frequency of the gate driver IC?