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Part Number: UCC27525
I'm using a UCC27525 gate driver IC to drive the mosfets being used in the CUK converter topology attached below. A dual mosfet is being used with a NMOS and a PMOS integrated in it. My question is that what is the safe voltage range for the VDD pin to be supplied with? What i supply the VDD with is a +8v. To drive the gate of a PMOS a negative pulse should be applied to the gate and that's why i used an extra circuitry other than external gate resistor circuits as shown in the file attached below. But the problem is that as the supply voltage applied to VDD pin goes up, the inductor current and output voltage waveforms become pretty noisy. The most stable voltage current waveforms were yielded with a +8v supply voltage and belowsch1212.pdf.
Secondly, what is the value of RNMOS for this gate driver IC. Based on the datasheet the effective resistance of the hybrid pullup structure during turn on is estimated to be approximately 1.5 × ROL, estimated based on design considerations. Where is this resistance used for in IOH calculation?
Third, what is the internal operating frequency of the gate driver IC?
Welcome back! Glad to see you're using UCC27525.
-This IC can be safely operated anywhere between 5V to 18V depending on your application needs. Can you please clarify why C6 and D1 at the driver's output and what specifically you're trying to accomplish?
If your application permits, you can certainly operate the device at 8V which should be enough to turn-on both FETs while giving you enough headroom from the UVLO threshold (4.5V).
-RNMOS is 1.5 x ROL where ROL = 1-Ohms, therefore RNMOS= 1.5-Ohms.
This is not a DC value as the N-ch FET is only turning on during a very brief moment around the miller region of the turn-on FET. The thread below discusses this:
Additionally, for IOH calculation, please refer to the document below:
Please let us know if you have further questions.
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In reply to Mamadou Diallo:
Thanks for your valuable feedback. To answer your question why I put C6 and D1 right in the output channel path, in order to excite the gate of the P-channel mosfet the gate signal should be of negative pulses (here pulse between 0 and -8). Without using that extra circuitry ( C6 and D1) both output channels generate positive pulses. The purpose of that circuitry is just to generate negative pulses by charging and discharging the capacitor (C6). The output voltage would be Vout = -Vc (voltage across C6) + Vin ( pulse signal between 0 and +8v). The picture attached below clarifies the purpose. My question is that would this approach work for the mentioned gate driver? In other words, is this approach gonna impact the gate driver (UCC27525) performance?
In reply to daniel sargezi:
Sorry I totally misread your initial post describing the purpose of the discrete circuitry.
My main concern is the voltage seen by the driver's output, keep in mind, the OUT pins cannot/ handle negative voltages higher than -0.3DC and no more than -2V as a 200ns pulse. Specifically in the event of surges at the gate, which could couple back to the driver's output stage.
The other concern that I have is the response time which will certainly impact your dead-time and synchronization of the 2 FETs because this will create a delay on the channel driving the P-CH while the N-Ch would be turn-on earlier.
have you simulated your circuit? If so, can you share your simulation results?
Thanks for your great response, you're totally right i got your point.But this the only way that a PMOS in this configuration can be driven because the source as you can see from the figure attached below is connected to ground so the gate has to be of a pulse between 0 and a negative value, correct me if i'm wrong please. Another question is that is it possible to use 2 N-channel mosfets in a CUK converter topology? I had a hard time driving the NMOS used as a synchronous switch in the CUK converter topology that's why i decided to use a PMOS.8625.sch1212.pdffigures.1TI.pdf
My apologies for the delayed response.
I have not seen a CUK converter topology with 2 N-ch FETs.
You could drive the P-channel FET depending on Vgs thresholds, using a positive voltage by connecting the drain of the P-ch FET to ground, while connecting the source to VDD of the gate driver IC. In that scenario, during high state of the signal gate signal = 12V, and Source voltage = 12V which means the P-ch FET is off. Second scenario is during low-signal, gate signal = 0V, and source voltage = 12V, => Vgs = 12V which means the P-ch FET is ON and conducting.
Alternatively, depending on required efficiency levels, you could use a discrete diode instead of the P-ch FET. The trade-off, as you might imagine is high power dissipation in your system caused by the the diode losses which would reduce the overall system efficiency.
Please let us know if you have further questions or press the green button if this addressed your inquiry.
Thanks so much, that helped a lot. I will get back to you with further questions regarding Gate driver design.
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