UCC27712: UCC27712 IC Problem

Hello Sinil,

thank you for the interest in the UCC27712 gate driver. I am an application engineer with the high power drivers group and will work to help resolve your concerns and questions.

Regarding the schematic referenced in the SPRABWOC app note. I do have some comments. Also to provide the best advice, can you provide schematics and layout of the driver and power train area?

The components selection for the UCC27712 driver depends on the power switch parameters, VDD voltage and switching frequency. The maximum on time of the HO output is also important. Refer to the UCC27712 datasheet Section 8.1 for design guidance.

The HB capacitance of 4.7uf shown in the schematic is a fairly large value, which may be needed if the HO on time can be very long. The total VDD capacitance is recommended to be 10x the HB capacitance so the 100nF shown close to the driver in the schematic is not adequate for bulk storage. But there is likely additional capacitance on the VDD line in this design. Review your values based on your design and the datasheet guidance. I would recommend a resistor in series with the boot diode to limit the diode peak charging current and impact on VDD voltage during charging.

Depending on your layout details, there can be ground bounce or induced noise on the driver inputs. I recommend provisions for a small R/C filter on the driver LI and HI inputs. Place the capacitors close to the driver LI/HI pins and COM pins. Depending on the power MOSFET Qg and the desired switching time the gate resistance can be adjusted to limit the power train switch node dV/dt. High dV/dt can result in excessive noise injected into the control signals and transients on the driver output pins.

Confirm if the driver input signals may have excessive noise which may false trigger the driver. Confirm that the driver pins are within the device ratings. And confirm if the driver outputs or HS pin has voltage overshoot or undershoot during operation.

If there are signals of concern, include the scope plots in the post and I can provide more detailed guidance.

Confirm if this addresses your concerns, or you can post additional questions on this thread.

Regards, 

Hello Sinal,

Here are my comments on the schematic review.

UCC27712 driver.

HB capacitance of 440nF for the MOSFET part number IPP80R360P7 with Qg of 30nC looks adequate for 20kHz operation. VDD capacitance of 4.7uF meets the recommendation of 10x boot capacitance. Use high quality dielectric ceramic such as X7R or better for VDD and HB capacitance. It is recommended to have a lower value ceramic such as 100nF in parallel which will provide improved high frequency filtering.

The boot diode MUR160 is a good choice. You may consider increasing the boot resistance to limit the dV/dt on HB cap during initial charging. Consider a 10 Ohm resistance to charge the 440nF capacitor.

The input filer values of 100 Ohms and 330pF looks like good initial values.

Gate resistance and MOSFET. The Q7 Mosfets are capable of fast switching speeds and has a high gate to drain Vs gate to source charge. This combination can result in significant miller charge coupled into the Vgs during switching. Also the body diode characteristics are poor if there will be body diode conduction. The trr is 1.1us which is very slow. Can you confirm if you are using C7 MOSFET’s for this application? The C7 are optimized for SMPS with no expected body diode conduction. The CFD series MOSFETs have much faster body diode recovery and will likely be better for this application. IGBT’s are commonly used for inverters.

If the C7 MOSFETs are used, I would suggest increasing the gate resistance and adding a gate to source capacitance at the MOSFET gate and source terminal to reduce the Vgs pertubations during switching.

UCC2720x driver,

VDD capacitance is OK, HB capacitance no value shown, 440nF will be OK based on IRFB4137 and assuming 20kHz operation.

Gate resistance, confirm HS dV/dt is within datasheet rating of 50V/ns with the 3.3 Ohm resistance.

Comments on Layout

UCC27712 Q6 and Q7:

The driver HS pin should be connected to the high side MOSFET source with as low inductance traces as possible. The U7 HS pin is connected closest to the low side drain, with a long trace from low side drain to high side source. Connect HS pin to Q8 source with a shorter trace length. For U6, increase trace width of high side MOSFET to driver HS pin where possible. The gate drive current loop from the driver to low side MOSFET is from driver output to MOSFET gate, and return path of MOSFET source to driver COM pin. The MOSFET source connection to input capacitance trace length (ground) looks very long and narrow. And the driver ground reference plane to input filter cap is not clear on the connection path. Ideally the MOSFET source will be connected to input capacitance with a low inductance connection, and driver ground is will referenced to MOSFET source. There is likely a lot of voltage ground bounce on the MOSFET source relative to the driver ground.

Confirm if this answers your questions, or you can post additional questions on this thread.

Regards,

Hello Sinal,

Thank you for the update on the status on the testing. With inverters applications it is possible to have current conduction in the MOSFET body diode and I see a noticeable difference in the IRFB20N50KPBF body diode trr of 520ns with If at 20A, and the IPP80R360P7 body diode trr of 1100ns with iF at 2.8A. If there is current flowing in the FET body diode, when the other bridge FET turns on there is effectively a short in the 2 FET’s until the body diode turns off. Very slow body diode recovery can result in high dI/dt when the body diode finally turns off. The much slower body diode recovery of the P7 MOSFET can result in higher stress in the MOSFETs and disturbance to the gate drive Vgs waveforms and also voltage transient stress to the driver outputs.

Question: Connect HS pin to Q8 source with a shorter trace length : Is it Q9?

Yes, it looks like Q9 source is connected to the HS pin of U7.

Question: Ideally the MOSFET source will be connected to input capacitance with a low inductance connection, and driver ground is will referenced to MOSFET source. : For U7 IC, ground Pin and Q8 Source are connected with short cable to avoid long loop as per your suggestions. Is it correct?

If there is a cable connecting the low side FETs source to the input filter capacitance, that would be a high parasitic inductance relative to a short/wide PWB trace.

Inverters and motor drive can have not as ideal layout as most power converters. A recommendation to reduce the ringing and disturbance of the VGS voltage at the MOSFET terminals is to add a ceramic capacitance close to the MOSFET pins. This will serve to add filtering of the VGS ringing from the long trace inductances.

Regarding the question on the recommendation of the FCPF400N60 or IPP65R310CFD MOSFETs.

Both parts are improved regarding the body diode trr with the FCPF400N60 at 240ns and the IPP65R310CFD of 95ns. The FCPF FET mentions solar inverters as a target application which is similar to yours. The IPP65R specifically mentions ideal for resonant topology, but the fast body diode should work well for your application. I think the FCPF FET is likely more cost effective and should work for your application.

With either FET, it looks like the gate charge is lower than the previous parts. You should re-evaluate the gate resistance since there may be higher dV/dt with these FETs.

Confirm if this addresses your questions, or you can post additional questions on this thread.

Regards,