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BQ25120A: BQ2512x Schematic Review Checklist

Raheem
Mastermind 21590 points

Part Number: BQ25120A

What are some key considerations when designing a BQ2512x schematic?

  • 0
    TI__Mastermind 21590 points

    BQ2512X Schematic Checklist

     

     Minimum of 1uF capacitance on IN pin to GND. Account for capacitor derating. Ensure capacitor is rated to twice input voltage.

    Connect minimum 3uF capacitance on PMID pin to GND. Account for capacitor derating. Ensure capacitor is rated to twice input voltage.

    Ensure USBGND and PGND are tied together.

    /CD pin is typically connected to MCU GPIO. Pin is internally pulled low with 900kΩ resistor. /CD is governed by table below.

    /CD State VIN Absent VIN Present
    Low Hi-Z Mode Charge Enabled
    High Active BAT Charge Disabled

    SDA pulled up VSYS with resistor

    SCL pulled up VSYS with resistor

    Connect appropriate resistor value to ILIM pin. The resistor value should be between 500Ω and 4kΩ.

    LSCTRL should be pulled either high or low depending on desired startup state. LDO can be disabled or enabled through I2C regardless of LSCTRL state. If LDO voltage is updated through I2C, LDO will need to be disabled and then enabled for voltage change to occur.

    Connect appropriate resistor value to ISET pin. The resistor value should be between 665Ω and 39.2kΩ.

    Connect appropriate resistor value to IPRETERM pin. The resistor value should be between 549Ω and 15kΩ.

    /INT is an open-drain status output that signals charging status and fault interrupts. Connect to an LED or pull up to VSYS (or external VIO) with 100KΩ resistor.

    /PG is an open-drain status output that signals Power Good status. /MR can be level shifted to /PG when PGB_MR but in register 0x08h is enabled. Connect to an LED or pull up to SYS(or external VIO) with 100KΩ resistor. Can be left floating if unused.

    /RESET is open drain active low in output. Pull up to VSYS (or external VIO) with 100kΩ resistor.

    /MR is pushbutton input that can be used to reset the device or count for wake timers. This pin is pulled up internally and can be left floating if functionality is not needed. Note that if /MR is not used, the only way to exit shipmode if through VIN insertion.

    Connect 2.2µH inductor to SW.

    Connect minimum of 10µF capacitance on SYS. Account for capacitor derating. Ensure capacitor is rated for twice SYS voltage.

    Connect minimum of 1µF to LS/LDO. Account for capacitor derating. Ensure capacitor is rated for twice LS/LDO voltage.

    Connect minimum of 1µF from VINLS to GND. Account for capacitor derating. Ensure capacitor is rated for twice SYS voltage. VINLS is typically connected to PMID.

    Connect minimum of 1µF from BAT to GND.  Account for capacitor derating. Ensure capacitor is rated for twice BAT voltage.

    Follow datasheet procedure on TS pin. If TS will NOT be used, set the TS in off mode with RHI = 37kΩ and RLO = 50kΩ with NTC thermistor absent. RHI should be pulled up to VIN.