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LM5105: Usage when LO output is short

Part Number: LM5105

We designed the Half-Bridge MOSFET Driver circuit using LM5105 as Figure 1.
We are trying to drive in 60Hz Acrive-Low, High-side 16.6ms and Low-side 1.8μs continuously.
And other information is described below.

VDRV_L: Referential voltage of this circuit (NOT GND)
VDRV_H: Min 5V, Max 15V (variable by user)
VDD: 12V
VSS: 0V (VDRV_L)
EN: 3.3V
DIN: High=3.3V, Low=0V

DOUT is not connected to any load.

We carried out actually such driving and found problems.
A waveform of DOUT falls very slowly.
It takes longer time than 1.8μs to be Low-level completely as Figure 2.
And HB voltage descends gradually in a High period as Figure 3.

What is the cause of these problems?
And, we would like to drive this circuit without DOUT slow falling down.
Do you have any idea to improve this situation?

Thank you.

<< Figure 1 >>

<< Figure 2>>

<< Figure 3 >>

  • Hello,

    Thank you for the interest in the LM5105. Reviewing the scope plots you provided, it looks like the DOUT time that is switching low is as expected at 1.8us but the voltage is not going low in the beginning. I want to confirm this is the concern.

    I have some questions in the application. The VDRV_L with a bias voltage should be OK if the low side MOSFET is referenced to this voltage, LM5105 VSS pin, and the driver input control signals are also referenced to this VDRV_L. The low side MOSFET should switch to this reference when the low side switch is turned on.

    One question. Is the scope plots ground reference to the VDRV_L voltage in the plots? Please confirm what the VDRV_ voltage waveform looks like compared to DOUT if the scope probes are referenced to ground. The VDRV_L voltage may not be DC during the switching.

    Also, I am curious about the function of R8 and R14 resistors connected between the MOSFETs drain and source. Confirm if the resistance is affecting the waveform.

    Confirm what the low side MOSFET drain signal looks like with the scope ground referenced to VDRV_L.

    Please confirm if this addresses your questions, or you can post additional questions on this thread.

    Regards,

  • Thank you for your reply!
    As you mentioned, our concern is that the DOUT is not going low enough in the beginning of switching low.

    Figure1 shows VDRV_L voltage[DC:-4V] and DOUT. Both are referenced to ground.
    VDRV_L looks a little noisy, but not so much distorted.

    Figure2 shows the low side MOSFET drain signal [D2] and DOUT.

    Also, we put R8 and R14 for prepending an overcurrent entering to MOSFET directly.
    But, in my opinion, these resistance are not so important and capable to be changed to 0 ohm resistance.

    Figure3 shows the low side MOSFET drain signal [D2] and DOUT with 0 ohm resistance on R8 and R14.
    DOUT reaches to low earlier than before.
    I think the situation looks to be rather improved, but not fundamentally.

    If you have other things to check, please tell me again.

    Thank you.

    << Figure1 >>

    << Figure2 >>

    << Figure3 >>

  • Hello,

    Thank you for the additional waveforms and some clarification on the voltage levels of VDRV_L relative to ground.

    It is still not clear why there is a delayed falling edge on DOUT if there is not a resistance or load on DOUT.

    Can you record the gate drive waveforms to confirm the VGS waveshape? G2 to S2 (same as VDRV_L). And G1 to S1, in this case S1 has R14 in series before VDRV_L, so you need to float this signal by itself.  

    Regards,