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TPS7A78: Output re-startup at Slow down mode(100ac to 0ac)

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Replies: 1

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Part Number: TPS7A78

Hello

My customer is evaluating TPS7A78EVM now. They have a question.

Could you please support the following question?

Customer comment is below,

 We do a slow-down test on TPS7A78EVM (Half-bridge mode) and can't understand a waveform under slow-down mode.
So we need an explanation from IC designer.

Test condition
Slow down conditon:   100V/0.5s
Start voltage: AC100V
loading conditions: 390Ω

What we are concerned about is why the LDO output voltage can be recovered under slow-down mode?

Thanks

Muk

  • Hi Mukono-san,

    I would need to see what is happening at SCIN and LDO_IN to be sure, but as the AC voltage falls the high voltage capacitor can no longer supply the full load current. If this happens, SCIN and LDO_IN will fall resulting in the output shutting down. Now that there is no load, LDO_IN will charge back up and once again turn on the LDO output.

    If this is happening, increasing the capacitance in SCIN should prevent this by providing additional hold-up energy.

    This is just a guess with seeing more detail. Can you supply wave-forms showing SCIN and LDO_IN when this is happening?

    John Cummings 蔣康明
    Texas Instruments 德洲儀器
    Johncummings@ti.com

    Please click the "Resolved" link at the bottom of this post if I have answered your question.

    Thank you,

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