**Part Number:** TPS548D22

Hi, we use TPS548D22 as the solution for V0.9_Vcore, which is shown as attached schematic.In total, it has 1uH inductor and 4*470uF electrolytic capacitors plus 5*100uF ceramic capacitors 5*22uF ceramic output capacitors. Unfortunately, Vout oscillate with such large output inductor and capacitor, which is shown as attached wave.

For more question, please see the link below:

The D-CAP3 compensation loop used in the TPS548D22 converter is sensitive to the L-C filter resonance frequency, and phase delay between the inductor current and the output voltage ripple. And it is said that it is hard to analyze loop stability of TPS548D22 with Loop Analysis.

With the help of TI FAE in China, we got the test result of our board from Loop Analysis in local TI lab. But, i'm still confused with something in the test wave.

1. for the figure above, waveform in the figure is different from the common loop analysis results. We are not sure if it matches the Bode plot of TPS548D22(DCAP3 mode controller).

2. can we judge if phase margin and gain margin are enough from bode plot ? because it's COT/DCAP3 mode controller.

3. can we conclude the loop instability of the circuit? What advice do you have for the loop stability with Loop Analysis?

4. if we use 1uH and R ramp compensation (now we use 1uH and 1/2R ramp compensation), no oscillation happened, can i think internal compensation work well and it's stable?

We did more tests and reduced the inductance to get the Bode Plot as follows. After changing 1uH to 470nH with R ramp compensation, no other changes, it seems the phase margin and gain margin obviously improved from bode plot. Does this mean that in our application, reducing the inductance of the inductor can improve the loop stability effectively?

looking forward to your reply. Let us know your email address for further communication. T

hank you.