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Part Number: TPS548D22
Hi, we use TPS548D22 as the solution for V0.9_Vcore, which is shown as attached schematic.In total, it has 1uH inductor and 4*470uF electrolytic capacitors plus 5*100uF ceramic capacitors 5*22uF ceramic output capacitors. Unfortunately, Vout oscillate with such large output inductor and capacitor, which is shown as attached wave.
For more question, please see the link below:
The D-CAP3 compensation loop used in the TPS548D22 converter is sensitive to the L-C filter resonance frequency, and phase delay between the inductor current and the output voltage ripple. And it is said that it is hard to analyze loop stability of TPS548D22 with Loop Analysis.
With the help of TI FAE in China, we got the test result of our board from Loop Analysis in local TI lab. But, i'm still confused with something in the test wave.
1. for the figure above, waveform in the figure is different from the common loop analysis results. We are not sure if it matches the Bode plot of TPS548D22(DCAP3 mode controller).
2. can we judge if phase margin and gain margin are enough from bode plot ? because it's COT/DCAP3 mode controller.
3. can we conclude the loop instability of the circuit? What advice do you have for the loop stability with Loop Analysis?
4. if we use 1uH and R ramp compensation (now we use 1uH and 1/2R ramp compensation), no oscillation happened, can i think internal compensation work well and it's stable?
We did more tests and reduced the inductance to get the Bode Plot as follows. After changing 1uH to 470nH with R ramp compensation, no other changes, it seems the phase margin and gain margin obviously improved from bode plot. Does this mean that in our application, reducing the inductance of the inductor can improve the loop stability effectively?
looking forward to your reply. Let us know your email address for further communication. T
Let me see if I can address your questions.
Yes. This is a typical waveform for a D-CAP2/3 control architecture. There is low phase and high gain at low frequencies where the control architecture drives to high DC set-point accuracy, some resonant peaking in the gain loop and phase drop from the L-C double pole resonance that is damned by the emulated ripple current, that is combined with a boost in the phase. Then there is a high frequency rise in the gain as the ESL of the output capacitors starts to dominate their total impedance.
Yes. The bode plot, measured in this way with the injected signal affecting both the FB voltage path and the VO sense path, is an effective way to measure the small-signal stability, as long as the injection level is kept to a few millivolts. Larger injection levels create skewed small signal measurements by driving non-linear loop response effects.
The phase plot dropping below 20 degrees in the no-load case is definitely concerning. This would be prone to oscillation during start-up when the converter needs to use all of the available loop gain to regulate the outputs voltage. Increasing the loop gain by:
1) Increasing the "R" of the R-C ramp injector level internally.
This will decrease the ramp slope while retaining the inductor ripple. That will decrease the emulated ESR and increase the emulated loop gain, increasing the cross-over frequency to a point where the phase has increased, improving stability and transient response.
2) Decrease Cout
This will increase the bandwidth of the loop response much in the same way as #1, but the reduced output capacitance will decrease the transient responds.
3) Decrease inductance.
Where Item #1 decreases the effective ESR by decreasing the voltage ramp slope, this decreases the emulated ESR by increasing the current ripple relative to the injected voltage ripple. Like item #1, this will both increase the bandwidth and increase the phase margin.
Changing the ramp generation resistor from 1/2R to R effectively doubles the loop gain, which should move the bode plot up 6dB.
It looks like it should be possible to move to 2*R, boosting the gain by 12dB, though the high-frequency gain is coming up high, which would drop the gain margin. Based on how high the gain is getting at very-high frequencies, it would appear there might be an issue with the high-frequency bypassing, ground impedance, or locating the remote sensing feedback point after the main capacitors where inductance in the power-path is adding to the loop impedance at higher frequencies.
Decreasing the high-frequency impedance to lower the gain between 1-5MHz looks like it would allow higher bandwidth and even better transient response.
Peter James Miller
New Product Development Engineer
Power Management - DC/DC Solutions - High Performance Solutions
Member Group Technical Staff 2008
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