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UCC27517: Pull-up voltage on IN- pin

Takeshi Sasaki
Expert 4480 points
Part Number: UCC27517

Hi team,

Could you give me advise if VDD (e.g. 12V) with pull up occurs on IN- pin or not? For example, can low voltage logic buffer (e.g. 3.3V) be connected to the IN-pin with VDD=12V?

Best regards,

Takeshi Sasaki

  • 0
    TI__Genius 13445 points

    Hello Takeshi, 

    Thanks for reaching out, my name is Mamadou DIallo, I will help address your concerns.

    It sounds like you're trying to use UCC27517 in an inverting configuration. If so, there few key considerations to take into account. 

    -Input thresholds: this driver has inputs thresholds of VIN_H = 2.2V (typ.) and VIN_L= 1.2V (typ.) meaning in an inverting configuration you need a logic buffer signal > 2.4V for the output stage to go low while you will need a logic buffer signal <1V for the output stage to go high. 

    -IN+ must be tied to VDD or an external supply (5V) for the inverting configuration.

    The table is (from the datasheet) is the truth table of the IC.

    Please let us know if this addresses your inquiry by pressing the green button or further post here if you have additional questions.

    Regards,

    -Mamadou

     

  • 0 in reply to Mamadou Diallo
    TI__Expert 4480 points

    Hi Mamadou,

    Thank you for your comments. It seems you've got different message that I want to ask. Simply speaking, can 3.3V logic buffer be connected to IN- pin when VDD=12V as follows? For UCC27517 functional block, IN- pin is pulled up to VDD pin, it seems VDD voltage will occur at IN- pin. 

    図1.tif

  • 0 in reply to Takeshi Sasaki
    TI__Genius 13445 points

    Hello Takeshi, 

    Thanks for the clarification. TO answer your question, yes the 3.3V logic PWM signal can be connected to IN- when VDD=12V as shown on the typical application diagram section of the datasheet.

    When IN- pin is left floating or unconnected, VDD internally pulls IN- high to ensure that the OUT remains low to prevent FET from turning-on. When a buffer is connected to any of the input pins, the logic PWM signal drives the input pins as the inputs are independent of the VDD voltage range.

    Please press the green button if this addressed your concerns.

    Regards,

    -Mamadou

  • 0 in reply to Mamadou Diallo
    TI__Expert 4480 points

    Hi Mamadou,

    Thank you for your reply. I understand. Thanks!

  • 0 in reply to Takeshi Sasaki
    TI__Expert 4480 points

    Hi Mamadou,

    Could you give me comments on following additional customer question in attached figure? In the customer system, VDD=12V is powered up first and 3.3V power supply is later than that due to power sequencing. I'm not sure how to prevent such situation, so if yes, could you give me advise on how to prevent such situation?

    Best regards,

    Takeshi Sasaki

    図2.tif

  • 0 in reply to Mamadou Diallo
    TI__Expert 4480 points

    Hi Mamadou,

    Could you give me comments on following additional customer question in attached figure? In the customer system, VDD=12V is powered up first and 3.3V power supply is later than that due to power sequencing. I'm not sure how to prevent such situation, so if yes, could you give me advise on how to prevent such situation?

    Best regards,

    Takeshi Sasaki7183.図2.tif

  • 0 in reply to Takeshi Sasaki
    TI__Genius 13445 points

    Hello Takeshi,

    I will respond to your inquiry before end of business day today.

    Thanks.

    Regards,

    -Mamadou

  • 0 in reply to Mamadou Diallo
    TI__Genius 13445 points

    Hello Takeshi,

    The INx pins are input pins and therefore do not source/sink enough current to damage the buffer's output stage. IN- is internally pulled HIGH only to allow internal logic to pull OUT pin low and shutdown the driver. 

    Please let us know if you have further questions.

    Regards,

    -Mamadou