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Original question:

TPS2121: TPS2121 reverse current and batteries

TPS2121: TPS2121

Cesare Conte
Prodigy 90 points
Part Number: TPS2121
Other Parts Discussed in Thread: TIDA-01638

Dear All,

I designed a power MUX stage using a TPS2121 and I' m facing sime problem.

Here below you can find the TPS2121 portion of the schematic

EXT_PWR is a 6V power source while USB_PWR is a 5V from a USB port. Priority is given to EXT_PWR ,SYS_PWR switch to USB_PWR when EXT_PWR is lower than 4.75V and return to EXT_PWR if this is higher than 5.25V.  Here below you can see what happens when USB_PWR is stable but  EXT_PWR is not stable.

If the time interval where EXT_PWR is long enough everything is fine and SYS_PWR switches correctly to USB PWR

Green: EXT_PWR 

Red : SYS_PWR

Yellow : PR1

Blue : ST

But if EXT_PWR drops at the same time of the rising edge of ST SYS_PWR do not switch to USB_PWR, it  drops to zero Volts and then restart with soft start

If EXT_PWR drops before the rising edge of ST SYS_PWR remain at USB_PWR without any drop.

Can you please suggest a trick to avoid the drop to 0V in SYS_PWR ?

Thanks in advance

Cesare Conte

  • 0 in reply to Cesare Conte
    TI__Mastermind 32650 points

    Hi Cesare,

    How is the IN1 being removed during switchover? 

    Do you have some control circuitry monitoring this?

  • 0 in reply to Shreyas Dmello
    Prodigy 90 points

    Hi Shreyas

    EXT_PWR is derived from an external 8..30V power source through a DC/DC converter that reduces the external voltage to a regulated 6V applied to IN1.

    The DC/DC converter has a power good open collector output which is open when EXT_PWR is in regulation and goes down when EXT_PWR is below 80% of the regulation voltage. The DC/DC converter has also a programmable EN level. Actually the PG output is not used and the TPS2121 works based on voltages.

    During the test where the TPS2121 fails to switch to USB_PWR, the external 12V power source is simply connected and disconnected through a relais controlled by a pulse generator  in order to simulate what would happen in case of an instable connection. VSYS_PWR is loaded wiith 3 Ohm load.

    Thanks

    Cesare Conte

  • 0 in reply to Cesare Conte
    TI__Mastermind 32650 points

    Hi Cesare,

    An initial observation is that the device is trying to soft start into an input that is then immediately being removed.

    Is there some known time that the input is "known good" for this sort of testing or are you purposely removing the input during this switchover?

    Could you please repeat the test as in the second scopeshot that you shared but please zoom into the timeframe where IN1 is removed. For this testing we would like to see: IN1, PR1, OUT, CP2

  • 0 in reply to Shreyas Dmello
    Prodigy 90 points

    Hi Shreyas,

    Please find here attached the tests at 100 msec/div as a reference and at 10 msec/div and 1 msec/div.

    Thanks in advance

    Cesare Conte

    Requested tests.pdf

  • 0 in reply to Cesare Conte
    Prodigy 90 points

    Hi Shreyas,

    I forgot to confirm you that I' m purposely removing the input during this switchover.

    Regards

    Cesare Conte

  • 0 in reply to Cesare Conte
    Prodigy 90 points

    Hi Shreyas,

    In the attached doc I added one more plot in which I replaced CP2 with ST in order to explain the rising edge on PR1,

    In this last plot you can see that when PR1 becomes equal to CP2 (3.3V) several things happens :

    • the slope of VIN1 (green trace) becomens much smaller menaing that current is no more drawn from VIN1
    • ST goes HIGH (Why ?) rising PR1 as if VIN1 is still present

    Regards

    Cesare Conte

    0537.Requested tests.pdf.

    Regards

    Cesare Conte

  • 0 in reply to Cesare Conte
    TI__Mastermind 32650 points

    Hi Cesare,

    I want to know what the minimaum known good time is for your input because then we can work on trying to switch faster. 

    Thank you for the further testing an block diagram. I have further questions:

    1. Why do you have a DC/DC on the output to provide CP2 voltage? If EXT_PWR is a stable 6V source, why not use a resistor divider to generate CP2? Can you also confirm if IN2 is indeed a stable source?

    2. What is causing your output to be pulled down to 0V so quickly? There is no integrated pull down on TPS2121. Do you have some other load on this system that is providing a discharge path?

    From the plots, it looks like the device is trying to soft start into an IN1 that is being removed. The output is unstable causing the DC/DC regulation to fail which pulls CP2 lower than 3.3V  This delays the switchover point. Then when PR1 finally drops below CP2, the device switches to IN2.

  • 0 in reply to Shreyas Dmello
    Prodigy 90 points

    Hi Shreyas,

    Regarding the minimum good time , please take into account that if EXT_PWR pulse is shorter the TPS2121 do not switch and everything works fine.

    1. CP2 is derived from main logical power which is derived from SYS_PWR (the output of the TPS2121) this configuration is taken from from TIDA-01638.  With reference to the schematics I sent you on the first post, the TPS2121 derive VIN2 power from an USB connector and VIN1 (EXT_PWR) from a DC/DC converter . during my tests VIN2 is stable while VIN1 is unstable. If the TPS2121 works well and switch correctly the CP2 voltage is stable at 3.3V. Beside this the VIN2 voltage is not constant: depending on the load and cable used the voltage can vary from 5.25 to less than 4 V.
    2. The output of the TPS2121 is loaded with a 3 Ohm load. You can see an inital fast drop on Vin1 (EXT_PWR) due to the fact that the capacitance on VIN1 is quickly discharged. Then the decay slope abruptly decrease because the TPS2121 VIN1 is no more loaded but outpot volatge drops because VIN2 is not supplying the output  .

    Regards

  • 0 in reply to Cesare Conte
    TI__Mastermind 32650 points

    Hi Cesare,

    The reason why we are looking for a minimum good time is because we can try to configure the soft start to get around this issue.

    Because your output is dropping, CP2 is dropping which in turn causes the device to switch over much later. I think it will be beneficial to use IN2 as the source for the 3.3V output. How stable is IN2 during this phase? If IN2 is not stable. is it possible to feed it through the 3.3V regulator?

  • 0 in reply to Shreyas Dmello
    Prodigy 90 points

    Hi Shreyas,

    I do not agree with your conclusions. I attached a new document that collect schematics  and the tests I already sent to you. Take a look at picture on page 5 : this picture shows the detail of a failed switchover from IN1 to IN2.

    As you can easily see CP2 (Blue trace) is still at 3.3V when the output of the TPS2121 (MAIN_PWR) drop to 0V. As a consequence of MAIN_PWR drop also CP2 drop but this happens 35 msec after the drop in MAIN_PWR.

    This is also clearly visible in the screenshot on page 6. In this picture you can also notice a strange behaviour of ST : look at the yello trace (PR1) and in particular at the sharp rise when PR1 drop to CP2. This is due to the feedback from ST and means that ST goes high also if PR1 < CP2. This is very strange and in my opinion should not happen. Note also that load current is not taken from IN1 (see the low slope ov voltage on IN1)

    Thanks

    Cesare Conte

    TPS2121 problem.pdf

  • 0 in reply to Shreyas Dmello
    Prodigy 90 points

    Hi Shreyas

    I do not agree with your conclusions.

    Take a look at page 5 of the attached document that contains all the screenshot I have already sent : the blue trace is CP2 and , as you can see , CP2 remain at 3.3V for more than 30 msec after MAIN_PWR (red trace), ie the TPS2121 output, drops to 0V. So when VIN1 drops CP2 is still stable at 3.3V.

    take also a look at the yellow trace at page 6. Yellow trace is PR1 and you can see that PR1 drops when VIN1 drops but, when PR1 drop to 3.3V there is a sharp increase in PR1 due to ST going high. Why ST goes high in this situation ?

    Regards

    Cesare ConteTPS2121 problem.docx

  • 0 in reply to Cesare Conte
    TI__Mastermind 32650 points

    Hi Cesare,

    So the file you just linked and the initial file have different schematics on them.

    I am going to assume that the older schematics are relevant as the scopeshots are the same (Oct 2nd)

    When IN1 comes up, the device moves into soft start mode. The device uses internal circuitry to regulate the soft start behavior. You are then removing the input which causes the device to soft start into nothing which causes this failure mode. The added hysteresis on the PR1 pin amplifies this issue as the voltage on PR1 doesn't cross the CP2 threshold. It is delayed by ST going high which changes the voltage divider network. The output voltage discharges faster than the input voltage can which then delays switchover more as CP2 droops due to output droop. To figure out a workaround for your system, we can  change the soft start behavior based on a "known good time". This may not be an option in your use case though so we will require more waveforms.

    We are very interested in the behavior during the event when ST goes from low to high. Is it possible to take scopeshots with a finer resolution around this event? We are also interested in the stability of IN2 during this phase.

    We would like two scopeshots around this event:

    1. IN2, VOUT, PR1, CP2

    2. ST, VOUT, PR1, CP2 

    Edit: Have you worked around your issue? Feel free to reply and we will continue support.