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TPS54332: ENable hysteresis vs output voltage

Intellectual 390 points

Replies: 8

Views: 209

Part Number: TPS54332

I am seeing a curious phenomenon in a circuit that uses a TPS54332 as the main regulator for a 6V rail, but which is backed up with a 5.5V LDO regulator (since the TPS54332 did not want to operate at 100% duty / pass-through mode). When the output rail is already at 5.5V the ENable threshold seems to move upwards - eg with 1.701V on the ENable pin, the TSP54332 still does not turn on, despite the typical ENable threshold being 1.25V and worst case 1.35V as per datasheet.

Is this expected behaviour from the part or should it still try to start up at 1.25V ENable voltage ?

If it is expected, then is there some documentation / design information which can be used to predict the actual ENable threshold ?

Best regards,


Patrick Herborn.

  • Hi,

    Could you please share the schematic and waveform? Let's see what happened.

    Shawn

  • In reply to Shawn Nie:

    Hiya Shawn!

    Thanks for picking up this ticket.

    In answer to your request, please find attached some screenshots of a PDF version of the schematic I have here. Note that there are two errors in the LDO40L section - the values there should yield 5.5V not 5V, and the resistors should be swapped over [that's how it is on the board, and that's what it does - generates 5.5V when the TPS54332 is not running, assuming enough input voltage of course].

    As regards waveforms, there aren't any because the TPS54332 is not turning on [the problem at hand]. When it does, the switching waveform looks sensible enough. If you need to see them then I can try to grab them with the DSO in the day. I am doubtful they will shed much light given that the problem is that the TPS54332 won't fire up, as opposed to running but not correctly.

    Many thanks,


    Pat.

  • In reply to Patrick Herborn:

    Hi Patrick,

    I can tell you with certainty there is no issue for the threshold voltage, please also share the layout for reviewing.

    Did you try to remove the backup regulator and check the issue?

    It would be better to show the waveform.

    Shawn

  • In reply to Shawn Nie:

    Hiya Shawn!

    Many thanks again for progressing this ticket.

    With regard to removing the backup regulator, that is something that I was not keen on doing to this board, so I have taken a slightly different approach which has nevertheless yielded some useful results / information. In order to drop the voltage on VCC6 down as much as possible prior to turn-on of the TPS54332 I removed one of the feedback resistors from the LDO40L. This resulted in VCC6 being sat at about 1.25V up until the TPS54332 starts up.

    I can confirm that with this modification, the TPS54332 fires up at 6.5V input voltage which, due to a Schottky diode between the input and the UVBAT rail (used for both reverse polarity and brownout protection - there is bulk capacitance on the TPS54332 supply rail) results in about 6.05V being present at the TPS54332's VIN pin. This should result in 1.164V present on the ENable pin, but in reality we get  1.262V which is interesting. The datasheet does mention some negative input current on the ENable pin, but even the 4uA would only account for 0.11mV across 27k4, not 98mV difference we see. The good news is of course that it is pretty much as per datasheet spec, turn-on at 1.25V (and well below the 1.35V max).

    With regard to the waveform, I have attached two - one at 6.6V into the board and one at 7.2V into the board. You can see that on the 6.6V into the board that the TPS54332 goes into stages of having the output on at 100% and then phases where it is very high duty - given the input voltage level of 6.05V when the board gets 6.5V in this is understandable - it will be slightly higher here but not much. With the input voltage up to 7.2V it becomes orderly and the pattern looks pretty sensible.

    With regard to the layout, I believe that the above test has conclusively proven that having near-desired output voltage already present on the TPS54332 does result in a change of the ENable threshold. That is perhaps not intended and/or not as per spec, it is however what it is doing and I'm not sure what benefit the layout will yield - ie I don't know what part of the layout could prevent the TPS54332 turning on until the ENable pin exceeds 1.7V.... but if this really is important then please advise whether it would be better to have a photo of that area, or a capture from the PCB CAD.

    As a final note - one issue we were having previously was the TPS54332 would "flap" when its input got too low. That is to say it would turn on, the output voltage would rise, then it would spend a while at pretty much 100% duty, but it would then give up. The output voltage would drop and then it would have another go. The present observation, whereby the threshold changes based on the output voltage (but perhaps only if this is down to external influence) might go some way to explaining that better - at the time I had just put it down to the device not liking 100% drive, either by design intervention in that instance, or by way of loss of bootstrap voltage for the highside transistor. I will do some testing to see if that is indeed the case and report back.

    Many thanks again,

    Pat.

  • In reply to Shawn Nie:

    Shawn,

    I submitted a reply to this, but it got flagged as requiring moderator approval, and the FAQ for that suggested that this was because the thread was solved and locked [which could conceivably happened whilst I was composing my post]. A refresh does not show this to be the case, so I don't know if that post has now been lost and I need to re-post it, or if it is indeed with a moderator.

    Best regards,

    Pat.

  • In reply to Patrick Herborn:

    Shawn,

    the fact that my previous post has now gone in proves the thread is not locked, and I will try again to post the answers to your questions :

    I was not keen on removing the LDO so I used a different method - I removed one of its feedback resistors so it would output only 1.25V rather than 5.5V. This change caused the TPS54332 to turn on with an input voltage to the board of 6.5V - the feed to the TPS54332 at that point was 6.05V, and the ENable pin was at 1.262V (though it should have been at 1.16V). Not sure why the ENable pin was seeing more than expected voltage - the negative input current specced on the datasheet would only account for a fraction of a millivolt, not the best part of 100mV. Regardless of that, it does turn on at the intended threshold of 1.25V when the LDO is not up near the desired voltage.

    I have attached two waveforms. One from 6.6V shows intermittent operation where sometimes it is at 100% and sometimes it is at very high duty. This is expected given that Vout is pretty much Vin. When we get to 7.2V into the board, it looks quite normal.

    With regard to the layout - I'm not sure how that will help, given that this test has now shown that changing the voltage present at the TPS54332 before it fires up does seem to affect its threshold voltage - this may not be intended / correct, but it is what is happening. If you really need the layout then please advise whether a photo or PCB CAD capture would be best.

    Many thanks,


    Pat.

  • In reply to Patrick Herborn:

    Hi Patrick,

    TPS54233 is nonsynchronous buck converter, and BOOT UVLO threshold voltage is about 2.1V, BOOT cap is connected to VIN via a diode internally,  the converter can start up until VIN is higher than about 2.1V+0.7V+5.5V(LDO)=8.3V, that is why the converter can't start up even if VIN gets to 6.5V(EN is 1.25V). Also that why I asked you to remove LDO to check this issue. When you remove the feedback resistor, LDO output voltage is lower, when VIN is higher than 6.5V, BOOT cap voltage is higher than 2.1V, the converter can start up normally.

    So if you want to add 5.5V LDO, it would be better to set VIN UVLO to be higher than 8.3V.

    Shawn

  • In reply to Shawn Nie:

    Hiya Shawn!

    First and foremost, *thank you* for your time, patience and perseverance! [I can appreciate this could have been a tad frustrating]

    Second, many thanks for pointing out what *should* have been obvious to me but which, for reasons to be explained, wasn't....

    There were two factors at play here : 1) not being able to see the wood for the trees, and 2) inability to apply the maxim that once one has eliminated the impossible whatever remains must be true. These factors were intertwined : the first "problem" I found was that ENable was higher than it should be, which was compounded by the fact I could not eliminate this as an impossible cause of the observed behaviour (past experience of bad silicon means I no longer assume it is right), so I found myself unable to move on. Lesson learnt - explore all options and eliminate in parallel not sequentially!

    This perfectly illustrates the value of support fora such as this in two ways : 1) insiders at TI will have access to information the rest of us don't and this could allow them determine that it was impossible for the ENable circuit to be the cause thus allowing the investigation to progress onto other possible causes and 2) others viewing the thread may have taken for granted (but without "proof") that the ENable circuit was working correctly, ergo the problem must lie elsewhere.

    With the benefit of the heads up of the 2.1V UVLO on the BOOT pin, it becomes clear that it is a chicken and egg scenario - the TPS54332 is simply unable to turn on the high side NMOS power FET (if it was PMOS then there would be no need for a BOOTstrap pin) - there's simply not enough delta-V across the bootstrap capacitor at this point. Once running, however, the flyback when the TPS54332 turns off its high side transistor allows the bootstrap capacitor to recharge, ergo it will quite happily keep running down to 6.1V into the device with 6V out. So rather than seeing some hysteresis on the ENable voltage (ie 1.7V to turn on in the first place), it was actually a hysteretic chicken/egg effect based around establishing, and maintaining enough delta-V across the bootstrap cap.

    With regard to the VIN UVLO, I'de prefer that the TPS54332 runs as soon as possible and I can think of a couple of ways that could be achieved :

    1) "Tickling" the inductor : TPS54332 is a 3.5A switcher, and we have a maximum of 20V input, ergo an 8R2 as the drain load of a transistor down to ground, which is able to pull the PH pin (and thus the flyback end of the inductor) could be used to charge the bootstrap capacitor and thus get the TPS54332 up and running. The resistor will limit the current to a safe level if the TPS54332 decides to turn on the high side transistor whilst the PH pin is being pulled low (ie short circuit prevention). This could be done from the processor that is ultimately powered by this switcher and which already can monitor the board input voltage. The danger (though I suspect slight) is that this will set up a reverse current in the inductor which will then fly back past VIN on the PH pin, BUT I would think that the body diode in the high side FET would clamp it at approx VIN+0.6V and that shouldn't cause any damage.

    2) A synchronous rectifier style isolation between the TPS54332 circuit and the rail it powers. This would allow plenty of delta-V across the bootstrap capacitor even if the LDO was supplying the circuit since the output of the TPS54332 would not be pulled up to 5.5V by the LDO. Rather than have a simple diode (and its associated drop and power wastage) a FET could couple the rails together. This would be slightly complicated by the fact that the FET should not turn on until quite close to 6V, otherwise once on it could stay on even if VIN dropped to the point of the TPS54332 shutting down and the LDO taking over, thus preventing a re-start of the TPS54332. 

    Many thanks again,


    Pat.

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