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UCC28780: PACKAGE SELECTION: SOIC-16 versus WQFN-16

Part Number: UCC28780

I am doing PCB layout for a design using the UCC28780.  The primary side circuitry is identical to the EVAL PCB: UCC28780EVM-002 using GaN.
I would like to use the SOIC-16 package because I think it will be easier for prototyping and troubleshooting, since the pins are exposed, and I don't need special soldering tools to desolder it.  
The EVAL PCB uses the WQFN-16 package.  I am nervous about using the SOIC-16 package because it seems that a lot of care went into the EVAL PCB layout (judging from the layout guidelines) and many nodes are critical due to the high switching speeds of the GaN devices.  Will I get into trouble using this package or should I be able to get it to work properly as long as I carefully follow the layout guidelines and good practices.  
If you think the SOIC-16 is too risky, I will use the WQFN-16. 
Thank you for your advice.

  • Hello Robert,

    Thank you for your interest in the UCC28780 ACF controller.

    There is no more layout risk using the SOIC-16 package than there is for the WQFN-16 package.  The SOIC pkg routing will require more room around the IC, of course, but there are some advantages of routing certain signals under the package that can't be done with the QFN. 

    In both cases care is necessary to prevent switching noise from interfering with sensitive signals.  Those signals are VS, SWS, RDM and RTZ.  Be sure that the node capacitances (to GND and to any other signal) of these signals are minimized.  Don't run a GND plane under them.  SWS does have a small cap on it, but that cap should return back to the current-sense resistor GND point, not directly to the local IC GND.  The opto-coupler collector-emitter loop should be parallel tracks from the opto to the IC to minimize noise pickup.  Keep away from high voltage switching nodes. 

    Since one of the usual goals for choosing this ACF controller is to achieve high-density power conversion, it can be a challenge to fit the controller in with the power conversion yet keep the high current paths separated so that the switching currents do not create GND-bounce or induce noise into control signals.  The layout guidelines and general good practices apply to both SOIC and QFN packages. 

    On piece of advice of personal preference: avoid defining a general ground-plane layer and then making numerous cut-outs and slots to steer current. Instead, I prefer to specifically route the return paths of switching currents and other loops using tracks to minimize loop areas.  That way I know exactly where the currents are going to minimize magnetic noise coupling.  And capacitive coupling from high switching dv/dt can be avoided.  Then later add Fill only in the "quiet" areas where necessary or convenient. 

    If you prepare your layout by carefully considering the effect each path will have on neighboring tracks and mitigating noise coupling, you can use the SOIC-16 package with confidence.

    Regards,
    Ulrich