• State Resolved
  • Locked Locked
  • Replies 3 replies
  • Answers 1 answer
  • Subscribers 61 subscribers
  • Views 662 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TPS3840: About startup behavior

Kaji@PAN
Mastermind 7840 points
Part Number: TPS3840


Hi,

I am FAE, a distributor of TI products.
I received a question about startup behavior from a customer.
The figure above is an excerpt from the data sheet. (TPS3840PL)
The figure below is an EVM excerpt. (TPS3840DL)

My customer's question is whether RESET goes Hi when VDD does not reach VIT + at startup.
At startup, the EVM waveform is RESET high for 62us when VDD is between 1.6V and VIT +.
This indicates that it takes some time for RESET to take effect at startup.
Does the same behavior occur when VDD is between VPOR and 1.6V or less?
Best regards,
  • 0
    TI__Genius 12630 points

    Hello FAE,

    The start-up behavior shown in Figure 13 shows the start-up behavior when VDD = VDD min and the corresponding time for /RESET to transistion to correct logic low. This is not the start-up delay that the EC table specifies which is from ramping VDD from below VDD(min) to 10% above VIT+ which is the correct test condition for the start-up delay measurement. I am working to update the Figure 13 in the User Guide to match the exact test condition used for "start-up" delay to prevent confusion. I expect to have the User Guide updated with correct Figure 13 by end of next week.

    Please let me know if you have any additional questions. Thanks

  • 0 in reply to Michael_DeSando
    Mastermind 7840 points
    Thank you for your reply.
    The customer wants to know if there is a condition for RESET to go high when VDD is below the VIT + threshold at startup.
    It would be helpful if you taught me the above contents.
    Best regards,
  • 0 in reply to Kaji@PAN
    TI__Genius 12630 points

    When using the active-low variants (TPS3840DL and TPS3840PL), there is no condition such RESET asserts logic high when VDD is below VIT+. Now there is a Vpor spec meaning the RESET output can get as high as the VOL  specified in the Vpor spec in table 7.5 in the datasheet. Once VDD rises above Vpor, then the RESET output is defined and in the correct logic state.