Part Number: TPS65132
My customer is having problem reading the I2C register, may I ask that is there any extra setting need to be done from the external to enable I2C control or reading?
Since they are also using LP8556, I2C should worked fine.
And they and also process write commend to TPS65132 by measuring the output of POS and NEG output.
Can you help to let us know the reason?
Please let us know if further information needed. I will help to confirm with customer.
Thanks a lot for your help.
Let me contact the expert for this part. You can expect a response by 10/30/19.
We are glad that we were able to resolve this issue, and will now proceed to close this thread.
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From your post, I infer that writing the I2C register of TPS65132 is working as output voltage changes occur as expected but reading the registers is is not working. Can you please, provide SDA/SCL waveforms? I will review to see if they reveal any anomaly. Also, what is the value of SDA/SCL pull up resistors and what voltage supply are they pulled up to?
In reply to Liaqat Khan:
It seems that the read comment doesn't reply the ack but write does reply, so we see failure on reading but not writing.
Please see below update for the waveform:
We read register address 0x00 and read back 0.(NACK)
We write register address 0x00 and success. (with ACK)
We read register address 0x01 and read back 0.(NACK)
Please let us know if this waveform helps or further information needed.
Great thanks for your help.
In reply to user021864:
Bit zero of the initial device address byte indicates whether this is write (bit0=0) or a read (bit0=1). If I am seeing the waveform correctly, bit 0 is 0 in the initial device address of all of the waveforms you attached. So this could be the problem. Please ensure that bit0=0 for write and bit0=1 for read.
Please see below capture for the the testing from RD
It seems not to be the problem of read and write.
The slave addressing for write and read transaction (0x7C and 0x7D respectively) is correct and for read transaction, the master generates a NACK at the end so this is all correct. Please note that at the end of read transaction, a NACK is supposed to generated by master and not an ACK. So I believe what you are getting is correct.
I am attaching a marked up picture of timing scope plot that I just captured and you can refer to it to debug this further if needed.
My customer is wondering if I2C read operation is correct, is there any reason to cause that read back data always is zero?
Can you help to give us some direction?
Thanks a lot.
I think we have discussed this enough on this forum and it appears that there is some system level issue causing the read back to be zero. I am closing this thread here and please look me up in directory services and send an e-mail message to further support.
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