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EM1402EVM: Forward Converter dynamics

Part Number: EM1402EVM
Other Parts Discussed in Thread: EMB1499Q

To whom it may concern,

I am working on the design of a custom BMS based on EMB1499Q driver. I'm trying to simulate in LTSpice the forward converter used in EM1402EVM both in forward (charging cell) and in current-fed (discharging cell) mode. In order to simulate the driver signals I set timing constraints suggested in the datasheet SNOSCV7B.
Using the values indicated in the datasheet (128uH and n=1.14 and Cclamp=0.022uF) I see a different behaviour of the converter and ZVS condition seems not to be verified in the forward mode. So I set different values for the capacitor and the transformer in order to obtain good results (1.28uH n=1.14 Cclamp=2.2uF).
On the other hand when I simulate the current-fed mode (with values indicated above), when HS1 and HS2 driver signals are in overlap, there is an irregular current charging the Cds of LS MOS and discharging the Cds of HS1 MOS during the rising edge of the driver signal of HS1 MOS.

Please find attached the simulation files. Is there a condition that isn't satisfied? 

Another problem is related to the use of the schmitt trigger inverter to emulate a turn on delay circuit for PWM_CLAMP signal: 
The BU4S584G2 used in the schematic (EM1402EVM) provides a delay in both rising and falling edge of the input signal (PWM_CLAMP) but in the application it is recommanded to delay only the falling edge. Is the BU4S584G2 used to only set a delay on the falling edge?

Thank you very much in advance for the support.


Best Regards,

MP

Simulation files:

/cfs-file/__key/communityserver-discussions-components-files/196/Simulations.7z

Irregular current (Discharge):

/cfs-file/__key/communityserver-discussions-components-files/196/Irregular-current.pdf

  • Hi Marco,

    Thank you for your thorough information! I would like to apologize in advance, as our ability to debug/support non-reference BMS systems based on the EM1402 is very limited. We also cannot utilize competitor simulation software, making this question a bit difficult.

    That being said, I will try my best to assist you with this.

    When looking at the plots you provided, if I understand it correctly, it appears that the overshoot is likely occurring due to the transformer chosen not fully discharging its energy between pulses (running in discontinuous mode). Likely, there is also no discharge path for the extra current in the simulation. So I would recommend adding a flyback diode to the input side of the simulation transformer. This may assist in removing the larger spikes from the simulation.

    To answer your second question, from a delay perspective, the BU4S584G2 is meant to provide a turn on delay, not just a rising/fall delay. It delays the entire pulse to delay the startup of certain parts of the circuit.

    I apologize that we cannot assist further on this, but let me know if the answers I have provided suffice!

    Regards,

    Vince

  • Hi Vince,

    I'm sorry for uploading competitor simulation files. However I resolved my issues but I've another problem about  the active clamp reset during the forward mode, using the configurations provided by Texas for the EM1402EVM (Lmag=128 uH and n=1.14 and Cclamp=0.022uF). Is the ZVS condition satisfied in designing this converter (before Qmain switches on and after Qaux switches on)? To verify this condition I refer to this relation: Lmag*MAX(Imag)^2>Cr*Vin^2. Is this the right disequation?

    Thank you for the reply.

    Regards,

    MP

    Schematic:

    /cfs-file/__key/communityserver-discussions-components-files/196/tidrn59a.pdf

  • Hi MP,

    The EM1402EVM is not designed specifically with ZVS in mind, particularly considering the "slow" 250 kHz switching frequency of the EMB1499Q.

    Let me know if this answers your question!

    Regards,

    Vince