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Original question:

TPS54360: Problem with Heavy Load using TPS54360 Reference Design

TPS54360: Noise on power supply from regulator near by.

jaice c mathew
Prodigy 190 points
Part Number: TPS54360

Hi,

I am using 2 TPS54360 for two different voltages.

please see the below schematics for the same .

When i load the regulator U1 with 2A, I am getting noise of >200mV on the other regulator output U6.

While removing the load from U1 , The noise from U6 get disappear.

Please let me know some solutions.

Schematics ;

Layout ,

U1 is on top and below that we had provided full GND reference .

Screenshot for layer 1;

Bottom layer ;

Layer 3 ,power layer 

Waveform for the U6 output .

Thanks,

Jaice

  • 0
    TI__Mastermind 27030 points

    Hi Mathew:

    for 200mV noise, is it switching noise ? can you help extend the the waveform to 10us/div.  U1 circuit has limited Cermaic Cap at output(C16), and it is far away in layer. how about 28V ripple at 2A, is it still larger? how about move C16 close to the chip.

    and you mentioned top layer is 28Vo, bottom is 5Vo, what is relative position of these two converters? 

    another suggestin is you can add some boot resistor to reduce the turn on speed of high side which maybe help you reduce the SW noise as well as its coupling to the output .

    pls also make sure the way you test the output ripple is using the smallest loop to test the ripple.

    Thanks

    Daniel Li

  • 0 in reply to Daniel Li14
    Prodigy 190 points

    Hello Daniel,

    Thanks for reply.

    Yes the waveform which i shown was switching noise on VCC_5.5V_PA rail.

    Please see the below recapture with 10us/div. for U6 ,VCC_5.5V_PA  rail with 1A load and 2A for U1.

    When i remove the load of other regulator ,ie; U1 , the noise get reduce 

    see the below image of U6, VCC_5.5V_PA rail with 1A load and no load on U1.

    See the below ripple for U1(VCC_28V_PA) with 2A.

    See the position of two regulators in top and bottom .

    Top is U1 in Green.

    U6 in Yellow .

    Thanks,

    Jaice

  • 0 in reply to jaice c mathew
    TI__Mastermind 27030 points

    Hi Jaice:

    thank you for providing detailed waveform and layout , we will discuss internally and give you feedback.

    one thing want to double check you is whether you use the min loop test the ripple shows as below? 

    Thanks

  • 0 in reply to Daniel Li14
    Prodigy 190 points

    Hello Daniel,

    Yes i had used mini loop test .

    Thanks,

    Jaice

  • 0 in reply to jaice c mathew
    TI__Mastermind 27030 points

    Hi Jaice:

    thank you for your confirm. below is our assumption:

    U1 SW has high dv/dt votlage which is in the same area of VCC_5.5V_PA .  it maybe coupled the dv/dt of SW from top layer to bottom layer.

    and in layer 3, i can't read out the each copper belong to. but if in the red rectangle, there is some copper connect to VC_5.5V_PA, the 5V output will be more easy couple the dv/dt of U1's SW.

    you can monitor the U1 SW with VC_5.5V_PA, and add RC snubber at U1 SW which can reduce the SW raise and fall slew rate and see see any improvement.

    second way is add boot resistors with C28 to reduce the high side turn on speed, it alos can reduce the SW raise slew rate.

    pls let me know whether it help. Thanks