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TPS3890: Sense Pin pull-up and pull-down values and MR input sensitivity

malli arjun1
Intellectual 610 points
Part Number: TPS3890
Other Parts Discussed in Thread: TPS3840

I am planning to use TPS389001 adjustable sense version to generate Power ON RESET to my ASIC.

I have 2 questions on this

My case:

VDD = 3.3V (comes 1st in power sequencing)

Vsense = 1.8V (comes 2nd in power sequencing)

MR = AND of ( 0.82V,1.0V,1.2V,3.3V, 2.5V, 0.6V(final rail) Open drain power goods)

My application,don't use any Manual RESET function, ONLY requirement is once all RAILS are in healthy state, need to send a RESET signal to ASIC.

1. To sense 1.8V for adjustable version,

Vitx(MON) = Vitx * (1+Rupper/Rlower) - (Equation1)

I see from Device comparison table from datasheet,

Vitn = 1.15V and Vitp = 1.157V.

Always Vitx(MON) is 1.8V,

By fixing Rlower = 100K, using equation1 Rupper is different for Vitn and Vitp.

Am i doing correct here ?

2. On the same lines as Question 1, datasheet sheet suggests(in Page 13) current through (Rtotal = Rupper+Rlower) should be Min 100times sense current.

sense current is in table mentioned as Max 8uA in one condition 100nA in another condition - These are not clear.

Which value needs to be taken as reference to calculate Rtotal.

3. I am connecting MR pin to combined (AND'ed) open drain Power good from all the rails.

All the regulators will be enabled at different instances,

My application,don't use any Manual RESET function, ONLY requirement is once all RAILS are in healthy state, need to send a RESET signal(configurable delay) to ASIC.

Is this device is intended for this kind of application?

4. if I don't want to use SENSE functionality, Is there any option to disable it?

 My application,don't use any Manual RESET function, ONLY requirement is once all RAILS are in healthy state, need to send a RESET signal(configurable delay) to ASIC.

Is there any simple Power ON reset generation device which has below requirements

1. VDD should be Min 1.8V Max at-least 3.3V, Should be sensitive to VDD >10% for generating RESET

2. Need to generate RESET pulse(configured delay from 100uS to >100mS) once MR pin is LOW as like TPS3890 does.

  • 0
    TI__Genius 9375 points

    Hi Malli,

    Let me explain and hopefully resolve your questions 1 by 1.

    1. This equation allows you to solve for either VITP or VITN based on what you desire to solve for. Let me give you an example. If I am monitoring a 3.3 V rail, and I want the VITN to be 2.93 V, I would be able to calculate the resistors as such:

    2.93 = 1.15 * (1+R1/R2)

    2.93 = 1.15 * (1+10k/R2)

    R2 = 6.46k

    I would then calculate VITP as:

    VHYST = [(VITP-VITN)/VITN] * 100%

    VHYST = [VITP-2.93V)/2.93V] * 100%

    0.575% = (VITP/2.93V - 1) * 100%

    1.00575 = VITP/2.93

    VITP = 2.947 V

    Hopefully you can use this example to further design your application.

    2. As you can see in table 7.5 (Electrical Characteristics), the input current on the sense pin is listed as 100 nA max for the adjustable version (TPS389001), so we should use this to design.

    3. Our devices are designed to be operated such that when devices are NOT in a healthy state, the supervisor issues a RESET. If you are looking for a RESET condition only when they are healthy, you may have to invert the logic. The MR pin will behave such that when it is pulled low, it will issue a RESET. This again, means that if you connect all the rails to an AND gate, feed it through to the MR, the RESET will be held low the entire time that MR is held low. When your rails are healthy, the device will exit RESET condition. You may have to invert the logic at the MR pin (use a NAND) such that when all rails are healthy and issuing a logic high (these will need to be monitored individually), they then issue a 0 to the MR, which resets the device.

    4. For this device, you can tie the SENSE pin to Vdd, and it will then just monitor the Vdd rail for changes in the voltage, but you will not be able to set the threshold and it will be internally set.

    In terms of other recommendations, it might be worth taking a look at the TPS3840 if you do not require a SENSE pin, and this may better suit your requirements.

    Thanks,
    Abhinav.

  • 0 in reply to Abhinav.Sharma
    Intellectual 610 points

    Hi Abhinav,

    Thanks for detailed explanation.

    1. I am clear on Vitp , Vitn calculations- I will calculate those values for my circuit configuration.

    2. Regarding Sense current, for 8uA row in datasheet there is no data on which device used(In general commonly applicable to all).

    As per your input, i am going ahead with Max current as 100nA.

    3. As you explained, I will tie all POWER GOODs to an AND gate and drive MR from AND gate output. So, that once all rails are healthy i will make ASIC comes out of RESET.

    Please confirm, once MR is LOW and then became HIGH(initial level LOW and then to HIGH), from MR became HIGH ==> RESET# signal LOW level will be delayed by time dictated by CT capacitor (So, that i will get Proper RESET to ASIC once all rails are UP)

    4. If i tie SENSE pin to VDD(3.3V), will the default levels be as per TPS389033 device.

    I can't go with TPS3840 as it is SOT23, I need a Lower package.

  • 0 in reply to malli arjun1
    TI__Genius 9375 points

    Hi Malli,

    I will try to better explain the conditions using this timing diagram from the datasheet:

    The way the interaction with MR and RESET works is shown here. When the device is in a good state on SENSE (healthy rail, not below threshold) AND MR is logic high, RESET will be logic high (not in reset). When MR is pulled low, RESET will go logic low after td(MR). This signal will then come back up to logic high after MR is pulled high after tPD(r). Use this to design your ASIC accordingly.

    For question 4, if you tie SENSE to 3.3 V, you must also design the VITP and VITN such that the VITN is 3.17 V using the correct resistors, and then the device will behave like TPS389033. If this is the case, however, just use that specific device.

    Thanks,
    Abhinav.