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UCC3813-1: Flyback Switching Frequency and Sync Duty Cycle Issues

Part Number: UCC3813-1
Other Parts Discussed in Thread: UCD3138, , UCD3138HSFBEVM-029

I am working with a UCD3138 hard switching full bridge evaluation module (UCD3138HSFBEVM-029). It uses a UCC3813-1 for the 3 housekeeping supply rails. Schematic available in the User Guide (http://www.ti.com/tool/UCD3138HSFBEVM-029#technicaldocuments). The flyback has a regulated 11V rail for the bridge gate drivers, an unregulated isolated 11V rail for the sync fet gate driver, and a 6V unregulated isolated rail from which 3.3V for the main controller is derived.

Issue #1: We are trying to synchronize the UCC3813 controller to an external signal. First off, I noticed the flyback was switching at 100kHz even though the Rt and Ct chosen should set the switching frequency to 200kHz per the datasheet. I found this odd. After successfully synchronizing the UCC3813 I found the flyback had a switching frequency of half my external sync signal. What's causing this? Is there something left out of the datasheet regarding the -1 variant of the UCC3813?

Issue #2: The datasheet suggests driving a 50 ohm resistor placed between Ct and ground with a 1V 100ns pulse width sync signal. This did not work for us. The datasheet states RC can also be driven directly by a pulse train. We removed Rt and Ct and applied our external sync signal directly to RC on the UCC3813. We are driving RC with a function generator that is more than capable of handling the low impedance state of RC while held high. What we notice is proper synchronization when the external sync signal positive pulse width is between 100-900ns (4-36% duty cycle @ 400kHz). If the external sync signal's duty cycle is increased above 35% we see the flyback output rails start to droop. This droop becomes detrimental nearing 45% DC and even causes the 3.3V LDO to dropout before reaching a duty cycle of 50%, causing the entire EVM to hiccup. Is this behavior to be expected? That datasheet does not specify this could be problematic but it may indeed be a limitation of the UCC3813. Any insight would be much appreciated.

For now we will focus on using a one-shot to reduce the pulse with for the UCC3813, but we want to verify if this behavior makes any sense or if something may be very wrong here. 

Thanks again,

Scott

  • Hi Scott,

    The UCC3813-1 expert will get back to you by tomorrow (1/14/2019).

    Best regards,

  • Hi Scott,

    The -1,4,5 variants of the device run at half the oscillator frequency see footnote 4 on page 5 of the datasheet.

    The SYNC pulse width should be 100ns, increasing the sync pulse width will limit the maximum duty cycle and may cause the power supply to lose regulation.

    The sync pulse needs to be sufficient in amplitude to trip the internal comparator on RC pin which has a typical threshold of 2.65V, see figure 16, page 14. The SYNC pulse gets added RC waveform, see figure 17 and causes the comparator to trip earlier that if it were to follow the waveform programmed by the Rt and Ct. That is why the controller can only be sync'ed to an external signal that is running at a higher switching frequency The Rt and Ct need to remain in circuit.

    If you are still having difficulties synchronising the controller please attached images of the sync signal source and the waveform on the RC pin.

    Regards

    Peter

  • Aha! I figured it was normal behavior and I was simply overlooking some details in the datasheet.

    I was successful in synchronizing using the universal technique as shown in Figure 19. The problem in my first attempt was likely not using a high enough pulse amplitude for how much higher frequency the external sync signal was compared to the set free running frequency. (400 kHz sync, 200 kHz free run)

    Thank you for your help.